IFIP TC6 Open Digital Library

VLSI-SoC 2012: Santa Cruz, CA, USA - Selected Papers

VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design - 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers

Andreas Burg, Ayse Kivilcim Coskun, Matthew R. Guthaus, Srinivas Katkoori, Ricardo Reis

Springer, IFIP Advances in Information and Communication Technology 418, ISBN: 978-3-642-45072-3


FPGA-Based High-Speed Authenticated Encryption System.

Michael Muehlberghuber, Christoph Keller, Frank K. Gürkaynak, Norbert Felber


A Smart Memory Accelerated Computed Tomography Parallel Backprojection.

Qiuling Zhu, Larry Pileggi, Franz Franchetti


Trinocular Stereo Vision Using a Multi Level Hierarchical Classification Structure.

Andy Motten, Luc Claesen, Yun Pan


Spatially-Varying Image Warping: Evaluations and VLSI Implementations.

Pierre Greisen, Michael Schaffner, Danny Luu, Val Mikos, Simon Heinzle, Frank K. Gürkaynak, Aljoscha Smolic


An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing.

Jeremy Constantin, Ahmed Yasir Dogan, Oskar Andersson, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues, David Atienza, Andreas Burg


Configurable Low-Latency Interconnect for Multi-core Clusters.

Giulia Beanato, Igor Loi, Giovanni De Micheli, Yusuf Leblebici, Luca Benini


A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks.

Zhibin Xiao, Bevan M. Baas


Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip Interconnections.

Anelise Kologeski, Caroline Concatto, Fernanda Lima Kastensmidt, Luigi Carro


On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors.

Davide Sabena, Luca Sterpone, Matteo Sonza Reorda


SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture.

Seokjoong Kim, Matthew R. Guthaus


CMOS Implementation of Threshold Gates with Hysteresis.

Farhad Alibeygi Parsan, Scott C. Smith


Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates.

Neil Di Spigna, Daniel Schinke, Srikant Jayanti, Veena Misra, Paul D. Franzon