IFIP TC6 Open Digital Library

VLSI-SoC 2006: Nice, France - Selected Papers

VLSI-SoC: Research Trends in VLSI and Systems on Chip - Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France

Giovanni De Micheli, Salvador Mir, Ricardo Reis

Springer, IFIP 249, ISBN: 978-0-387-74908-2


Architectures for High Dynamic Range, High Speed Image Sensor Readout Circuits.

Sam Kavusi, Kunal Ghosh, Abbas El Gamal


Oversampled Time Estimation Techniques for Precision Photonic Detectors.

Robert K. Henderson, Bruce Rae, David R. Renshaw, Edoardo Charbon


Innovative Optoeletronic Approaches to Biomolecular Analysis with Arrays of Silicon Devices.

Carlotta Guiducci, Claudio Stagni, M. Brocchi, Massimo Lanzoni, Bruno Riccò, A. Nascetti, Davide Caputo, A. De Cesare


Electronic Detection of DNA Adsorption and Hybridization.

Ulrich Bockelmann


Probabilistic amp; Statistical Design - the Wave of the Future.

Shekhar Borkar


A CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs.

Shan Jiang, Manh Anh Do, Kiat Seng Yeo


Probabilistic Design: A Survey of Probabilistic CMOS Technology and Future Directions for Terascale IC Design.

Lakshmi N. Chakrapani, Jason George, Bo Marr, Bilge E. S. Akgul, Krishna V. Palem


Reliability Issues in Deep Deep Submicron Technologies: Time-Dependent Variability and its Impact on Embedded System Design.

Antonis Papanikolaou, Hua Wang, Miguel Miranda, Francky Catthoor, Wim Dehaene


Soft Error Resilient System Design through Error Correction.

Subhasish Mitra, Ming Zhang, Norbert Seifert, T. M. Mak, Kee Sup Kim


Library Compatible Variational Delay Computation.

Luís Guerra e Silva, Zhenhai Zhu, Joel R. Phillips, L. Miguel Silveira


A Power-Efficient Methodology for Mapping Applications on Multi-Processor, System-on-Chip Architectures.

Giovanni Beltrame, Donatella Sciuto, Cristina Silvano


Frequency and Speed Setting for Energy Conservation in Autonomous Mobile Robots.

Jeff Brateman, Changjiu Xian, Yung-Hsiang Lu


Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation.

Zeynep Toprak Deniz, Yusuf Leblebici, Eric A. Vittoz


Logic Synthesis of EXOR Projected Sum of Products.

Anna Bernasconi, Valentina Ciriani, Roberto Cordone


A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits.

Renato Fernandes Hentschke, Sandro Sawicki, Marcelo de Oliveira Johann, Ricardo Reis


CAT Platform for Analogue and Mixed-Signal Test Evaluation and Optimization.

Ahcène Bounceur, Salvador Mir, Luís Rolíndez, Emmanuel Simeu


Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation.

Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara


Comparison of an Æthereal Network on Chip and Traditional Interconnects - Two Case Studies.

Arno Moonen, Chris Bartels, Marco Bekooij, René van den Berg, Harpreet Bhullar, Kees Goossens, Patrick Groeneveld, Jos Huisken, Jef L. van Meerbergen


Designing Routing and Message-Dependent Deadlock Free Networks on Chips.

Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo


Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model.

Ittetsu Taniguchi, Keishi Sakanushi, Kyoko Ueda, Yoshinori Takeuchi, Masaharu Imai


Human++: Emerging Technology for Body Area Networks.

Julien Penders, Bert Gyselinckx, Ruud J. M. Vullers, Olivier Rousseaux, Mladen Berekovic, Michael De Nil, Chris Van Hoof, Julien Ryckaert, Refet Firat Yazicioglu, Paolo Fiorini, Vladimir Leonov