IFIP TC6 Open Digital Library

VLSI-SoC 2005: Perth, Australia

VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia

Ricardo Augusto da Luz Reis, Adam Osseiran, Hans-Jörg Pfleiderer

Springer, IFIP 240, ISBN: 978-0-387-73660-0


Molecular Electronics - Devices and Circuits Technology.

Paul D. Franzon, David Nackashi, Christian Amsinck, Neil Di Spigna, Sachin Sonkusale


Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals.

G. Fraidy Bouesse, Marc Renaudin, Gilles Sicard


A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures.

Leonardo Londero de Oliveira, Cristiano Santos, Daniel Lima Ferrão, Eduardo A. C. da Costa, José C. Monteiro, João Baptista dos Santos Martins, Sergio Bampi, Ricardo Augusto da Luz Reis


Defragmentation Algorithms for Partially Reconfigurable Hardware.

Markus Koester, Heiko Kalte, Mario Porrmann, Ulrich Rückert


Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits.

Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin


3D-SoftChip: A Novel 3D Vertically Integrated Adaptive Computing System.

Chul Kim, A. M. Rassau, Stefan Lachowicz, Saeid Nooshabadi, Kamran Eshraghian


Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms.

Alberto Donato, Fabrizio Ferrandi, Massimo Redaelli, Marco D. Santambrogio, Donatella Sciuto


A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis.

Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici


Issues in Model Reduction of Power Grids.

João M. S. Silva, L. Miguel Silveira


A Traffic Injection Methodology with Support for System-Level Synchronization.

Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen


Pareto Points in SRAM Design Using the Sleepy Stack Approach.

Jun-Cheol Park, Vincent John Mooney III


Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs.

César A. M. Marcon, José Carlos S. Palma, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Ricardo Augusto da Luz Reis


Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping.

Jerome Quartana, Laurent Fesquet, Marc Renaudin


A Novel MicroPhotonic Structure for Optical Header Recognition.

Muhsen Aljada, Kamal Alameh, Adam Osseiran, Khalid Al-Begain


Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint.

Erik Larsson, Stina Edbom


On-chip Pseudorandom Testing for Linear and Nonlinear MEMS.

Achraf Dhayni, Salvador Mir, Libor Rufer, Ahcène Bounceur


Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles.

Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault


On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction.

Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner


Exact BDD Minimization for Path-Related Objective Functions.

Rüdiger Ebendt, Rolf Drechsler


Current Mask Generation: an Analog Circuit to Thwart DPA Attacks.

Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Michel Robert, Guy Cathebras, Gilles Sassatelli, Fernando Gehm Moraes


A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming.

Cristiano Lazzari, Lorena Anghel, Ricardo Reis