Filter your results
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
|
|
|
sorted by
|
|
|
Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings24th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSISOC), Sep 2016, Tallinn, Estonia. pp.108-129, ⟨10.1007/978-3-319-67104-8_6⟩
Conference papers
hal-01675192v1
|