%0 Conference Proceedings
%T Transformative Hardware Design Following the Model-Driven Architecture Vision
%+ Infineon Technologies AG [Neubiberg]
%+ Technische Universität Munchen - Technical University Munich - Université Technique de Munich (TUM)
%A Han, Zhao
%A Rutsch, Gabriel
%A Wang, Deyan
%A Li, Bowen
%A Prebeck, Sebastian, Siegfried
%A Lopera, Daniela, Sanchez
%A Devarajegowda, Keerthikumara
%A Ecker, Wolfgang
%< avec comité de lecture
%@ 978-3-031-16817-8
%( IFIP Advances in Information and Communication Technology
%B 29th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC)
%C Singapore, Singapore
%Y Victor Grimblatt
%Y Chip Hong Chang
%Y Ricardo Reis
%Y Anupam Chattopadhyay
%Y Andrea Calimera
%I Springer Nature Switzerland
%3 VLSI-SoC: Technology Advancement on SoC Design
%V AICT-661
%P 49-70
%8 2021-10-04
%D 2021
%R 10.1007/978-3-031-16818-5_3
%K Electronic design automation
%K Aspect-oriented programming
%K Model-driven architecture
%Z Computer Science [cs]Conference papers
%X Despite the high configurability of IPs and hardware generators, code modifications are still required to introduce aspect-oriented instrumentation to satisfy emerging aspectual design requirements such as on-chip debug and functional safety. These code modifications escalate development, verification efforts, and deteriorate code reuse. This paper proposes a highly efficient transformative hardware design methodology that leverages graph-grammar-based model transformations. Following the proposed methodology, main design functionalities and aspectual instrumentation are separately developed, automatically integrated, and verified. To demonstrate the applicability, industrial SoCs were transformed to support on-chip debug. Compared to the manual RTL coding, the proposed transformative methodology needed less than 32x Lines of Code (LoC) to develop and integrate the aspectual instrumentation. In particular, our approach enables high code reusability, as the implementation of the transformation script is a one-time effort, and can be applied to all evaluated SoCs. This high LoC gain and code reuse promote the overall productivity of digital design.
%G English
%Z TC 10
%Z WG 10.5
%2 https://inria.hal.science/hal-04419577/document
%2 https://inria.hal.science/hal-04419577/file/538103_1_En_3_Chapter.pdf
%L hal-04419577
%U https://inria.hal.science/hal-04419577
%~ IFIP
%~ IFIP-AICT
%~ IFIP-TC
%~ IFIP-WG
%~ IFIP-VLSISOC
%~ IFIP-TC10
%~ IFIP-WG10-5
%~ IFIP-AICT-661