%0 Conference Proceedings
%T SIRM: Shift Insensitive Racetrack Main Memory
%+ Tsinghua University [Beijing] (THU)
%+ Hangzhou Dianzi University (HDU)
%A Zhang, Hongbin
%A Wei, Bo
%A Lu, Youyou
%A Shu, Jiwu
%Z Part 8: Short Papers
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B 16th IFIP International Conference on Network and Parallel Computing (NPC)
%C Hohhot, China
%Y Xiaoxin Tang
%Y Quan Chen
%Y Pradip Bose
%Y Weiming Zheng
%Y Jean-Luc Gaudiot
%I Springer International Publishing
%3 Network and Parallel Computing
%V LNCS-11783
%P 355-360
%8 2019-08-23
%D 2019
%R 10.1007/978-3-030-30709-7_33
%K Racetrack memory
%K Shift insensitive
%K Main memory
%Z Computer Science [cs]Conference papers
%X Racetrack memory (RM) is a potential DRAM alternative due to its high density and low energy cost and comparative access latency with SRAM. On this occasion, we propose a shift insensitive racetrack main memory architecture SIRM. SIRM provides uniform access latency to upper system, which make it easy to be managed. Experiments demonstrate that RM can outperform DRAM for main memory design with higher density and energy efficiency.
%G English
%Z TC 10
%Z WG 10.3
%2 https://inria.hal.science/hal-03770574/document
%2 https://inria.hal.science/hal-03770574/file/486810_1_En_33_Chapter.pdf
%L hal-03770574
%U https://inria.hal.science/hal-03770574
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-TC
%~ IFIP-TC10
%~ IFIP-NPC
%~ IFIP-WG10-3
%~ IFIP-LNCS-11783