@inproceedings{wang:hal-03770552,
  TITLE = {{PRTSM: Hardware Data Arrangement Mechanisms for Convolutional Layer Computation on the Systolic Array}},
  AUTHOR = {Wang, Shuquan and Wang, Lei and Li, Shiming and Shuo, Tian and Guo, Shasha and Kang, Ziyang and Zhang, Shuzheng and Xu, Weixia},
  URL = {https://inria.hal.science/hal-03770552},
  NOTE = {Part 3: Neural Networks},
  BOOKTITLE = {{16th IFIP International Conference on Network and Parallel Computing (NPC)}},
  ADDRESS = {Hohhot, China},
  EDITOR = {Xiaoxin Tang and Quan Chen and Pradip Bose and Weiming Zheng and Jean-Luc Gaudiot},
  PUBLISHER = {{Springer International Publishing}},
  SERIES = {Network and Parallel Computing},
  VOLUME = {LNCS-11783},
  PAGES = {69-81},
  YEAR = {2019},
  MONTH = Aug,
  DOI = {10.1007/978-3-030-30709-7\_6},
  KEYWORDS = {DNN ; FPGA ; Systolic array ; Hardware data arrangement},
  PDF = {https://inria.hal.science/hal-03770552/file/486810_1_En_6_Chapter.pdf},
  HAL_ID = {hal-03770552},
  HAL_VERSION = {v1},
}