%0 Conference Proceedings
%T HiPower: A High-Performance RDMA Acceleration Solution for Distributed Transaction Processing
%+ Guizhou University (GZU)
%+ Department of Computer Science and Technology (CST)
%+ CETC Big Data Research Institute Co. Ltd
%A Zhang, Runhua
%A Cheng, Yang
%A Geng, Jinkun
%A Wang, Shuai
%A Gao, Kaihui
%A Shen, Guowei
%Z Part 5: HPC
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B 16th IFIP International Conference on Network and Parallel Computing (NPC)
%C Hohhot, China
%Y Xiaoxin Tang
%Y Quan Chen
%Y Pradip Bose
%Y Weiming Zheng
%Y Jean-Luc Gaudiot
%I Springer International Publishing
%3 Network and Parallel Computing
%V LNCS-11783
%P 209-221
%8 2019-08-23
%D 2019
%R 10.1007/978-3-030-30709-7_17
%K RDMA
%K Distributed transaction processing
%K Batched confirmation
%K One-by-one confirmation
%Z Computer Science [cs]Conference papers
%X The increasing complex tasks and growing size of data have necessitated the application of distributed transaction processing (DTP), which decouples tasks and data among multiple nodes for jointly processing. However, compared with the revolutionary development of computation power, the network capability falls relatively behind, leaving communication as a more distinct bottleneck. This paper focuses on the recent emerging RDMA technology, which can greatly improve communication performance but cannot be well exploited in many cases due to improper interactive design between the requester and responder. Our research finds that the typical implementation of confirming per work request (CPWR) triggers considerable CPU involvement, which further degrades the overall performance of RDMA communication. Targeting at this, we propose HiPower, which leverages a batched confirmation scheme with lower CPU utilization, to improve high-frequency communication efficiency. Our experiments show that, compared with CPWR, HiPower can improve the communication efficiency by up to 75% and reduce CPU cost by up to 79%, which speeds up the overall FCT (Flow Completion Time) by up to 14% on real workflow (Resnet-152).
%G English
%Z TC 10
%Z WG 10.3
%2 https://inria.hal.science/hal-03770544/document
%2 https://inria.hal.science/hal-03770544/file/486810_1_En_17_Chapter.pdf
%L hal-03770544
%U https://inria.hal.science/hal-03770544
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-TC
%~ IFIP-TC10
%~ IFIP-NPC
%~ IFIP-WG10-3
%~ IFIP-LNCS-11783