%0 Conference Proceedings
%T A Hierarchical Model of Control Logic for Simplifying Complex Networks Protocol Design
%+ College of Computer Science [Changsha]
%A Yang, Yi
%A Quan, Wei
%A Yan, Jinli
%A Tang, Lu
%A Sun, Zhigang
%Z Part 3: Algorithm
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B 17th IFIP International Conference on Network and Parallel Computing (NPC)
%C Zhengzhou, China
%Y Xin He
%Y En Shao
%Y Guangming Tan
%I Springer International Publishing
%3 Network and Parallel Computing
%V LNCS-12639
%P 182-187
%8 2020-09-28
%D 2020
%R 10.1007/978-3-030-79478-1_16
%K Finite state machine
%K Control logic
%K Network protocol
%K Hierarchical design
%Z Computer Science [cs]Conference papers
%X With the increase of network protocols complexity, the finite state machine model commonly used in hardware design is difficult to directly describe and manage complex protocol control logic. The hierarchical approach can simplify the design and implementation of complex logic. However, the control logic of the protocol is a whole, and how to divide the control logic of the protocol hierarchically is a problem that needs to be solved urgently. Therefore, by analyzing the characteristics of complex protocol control logic, this paper proposes the DoubleDeck model. This model divides the state in protocol processing into a global state perceivable by the protocol peer and a local state invisible to the outside. Next, we established a prototype system of the time synchronization protocol (AS6802) on the FPGA array based on the DoubleDeck model, which effectively verified the feasibility of the model.
%G English
%Z TC 10
%Z WG 10.3
%2 https://inria.hal.science/hal-03768758/document
%2 https://inria.hal.science/hal-03768758/file/511910_1_En_16_Chapter.pdf
%L hal-03768758
%U https://inria.hal.science/hal-03768758
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-TC
%~ IFIP-TC10
%~ IFIP-NPC
%~ IFIP-WG10-3
%~ IFIP-LNCS-12639