%0 Conference Proceedings
%T CompressedCache: Enabling Storage Compression on Neuromorphic Processor for Liquid State Machine
%+ College of Computer Science [Changsha]
%+ College of Computer Science and Technology [Hangzhou]
%A Yang, Zhijie
%A Gong, Rui
%A Qu, Lianhua
%A Kang, Ziyang
%A Luo, Li
%A Wang, Lei
%A Xu, Weixia
%Z Part 9: Storage
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B 17th IFIP International Conference on Network and Parallel Computing (NPC)
%C Zhengzhou, China
%Y Xin He
%Y En Shao
%Y Guangming Tan
%I Springer International Publishing
%3 Network and Parallel Computing
%V LNCS-12639
%P 437-451
%8 2020-09-28
%D 2020
%R 10.1007/978-3-030-79478-1_37
%K Spiking neural network
%K Neuromorphic processor
%K Liquid state machine
%K Storage compression
%Z Computer Science [cs]Conference papers
%X Spiking Neural Network (SNN) based neuromorphic processors have gained momentum due to their high energy efficiency. As a kind of SNN, Liquid State Machine (LSM) shows potential in domains such as image recognition and speech recognition, and it is simpler to train than other SNNs. In neuromorphic processors, weights and synapses are stored on-chip to reduce the energy cost of data movement. However, the storage of them is redundant if the dep loyed network on the neuromorphic processor is LSM which is a sparse SNN. By exploiting the sparsity of LSM, adopting storage compression can reduce the power consumption of the processor or enable a single chip to deal with more complex tasks with more logic neurons. In this work, we propose a lossy storage compression method, Compressed Sparse Set Associative Cache (CSSAC) which makes use of the sparsity and the robustness of LSM. We apply CSSAC on an LSM-oriented neuromorphic processor to demonstrate how the hardware design supports CSSAC to enable storage compression and complete LSM computation. CSSAC does not introduce much metadata overhead to ensure the compression effect, nor does it decrease the accuracy of LSM or the performance of the processor. Experimental results show that in our implementation, CSSAC can, at best, result in 14%–55% reduction in on-chip storage and 5%–46% reduction in power consumption of the processor under different weight data widths on MNIST, NMNIST, DVS128 Gesture datasets.
%G English
%Z TC 10
%Z WG 10.3
%2 https://inria.hal.science/hal-03768733/document
%2 https://inria.hal.science/hal-03768733/file/511910_1_En_37_Chapter.pdf
%L hal-03768733
%U https://inria.hal.science/hal-03768733
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-TC
%~ IFIP-TC10
%~ IFIP-NPC
%~ IFIP-WG10-3
%~ IFIP-LNCS-12639