%0 Conference Proceedings
%T RAT: A Lightweight Architecture Independent System-Level Soft Error Mitigation Technique
%+ Instituto de Informática [Porto Alegre]
%+ Wolfson School of Mechanical and Manufacturing Engineering
%A Gava, Jonas
%A Reis, Ricardo
%A Ost, Luciano
%< avec comité de lecture
%( IFIP Advances in Information and Communication Technology
%B 28th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC)
%C Salt Lake City, UT, United States
%Y Andrea Calimera
%Y Pierre-Emmanuel Gaillardon
%Y Kunal Korgaonkar
%Y Shahar Kvatinsky
%Y Ricardo Reis
%I Springer International Publishing
%3 VLSI-SoC: Design Trends
%V AICT-621
%P 235-253
%8 2020-10-06
%D 2020
%R 10.1007/978-3-030-81641-4_11
%K Multicore
%K Soft error reliability
%K Mitigation technique
%K Fault tolerance
%Z Computer Science [cs]Conference papers
%X To achieve a substantial reliability and safety level, it is imperative to provide electronic computing systems with appropriate mechanisms to tackle soft errors. This paper proposes a low-cost system-level soft error mitigation technique, which allocates the critical application function to a pool of specific general-purpose processor registers. Both the critical function and the register pool are automatically selected by a developed profiling tool. The proposed technique was validated through more than 400K fault injections considering a Linux kernel, different benchmarks, and two multicore Arm processor architectures (ARMv7-A and ARMv8-A). Results show that our technique significantly reduces the code size and performance overheads while providing soft error reliability improvement compared with the Triple Modular Redundancy (TMR) technique.
%G English
%Z TC 10
%Z WG 10.5
%2 https://inria.hal.science/hal-03759727/document
%2 https://inria.hal.science/hal-03759727/file/512096_1_En_11_Chapter.pdf
%L hal-03759727
%U https://inria.hal.science/hal-03759727
%~ IFIP
%~ IFIP-AICT
%~ IFIP-TC
%~ IFIP-WG
%~ IFIP-VLSISOC
%~ IFIP-TC10
%~ IFIP-WG10-5
%~ IFIP-AICT-621