@inproceedings{atishay:hal-03476608,
  TITLE = {{A Statistical Wafer Scale Error and Redundancy Analysis Simulator}},
  AUTHOR = {Atishay, Atishay and Gupta, Ankit and Sonawat, Rashmi and Thacker, Helik Kanti and Prasanth, B.},
  URL = {https://inria.hal.science/hal-03476608},
  BOOKTITLE = {{27th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC)}},
  ADDRESS = {Cusco, Peru},
  EDITOR = {Carolina Metzler and Pierre-Emmanuel Gaillardon and Giovanni De Micheli and Carlos Silva-Cardenas and Ricardo Reis},
  PUBLISHER = {{Springer International Publishing}},
  SERIES = {VLSI-SoC: New Technology Enabler},
  VOLUME = {AICT-586},
  PAGES = {139-163},
  YEAR = {2019},
  MONTH = Oct,
  DOI = {10.1007/978-3-030-53273-4\_7},
  KEYWORDS = {Redundancy analysis algorithm ; Defect simulation ; Error analysis ; Statistical modeling ; Wafer simulation},
  PDF = {https://inria.hal.science/hal-03476608/file/501403_1_En_7_Chapter.pdf},
  HAL_ID = {hal-03476608},
  HAL_VERSION = {v1},
}