%0 Conference Proceedings
%T Security Aspects of Real-Time MPSoCs: The Flaws and Opportunities of Preemptive NoCs
%+ Universidade Federal do Rio Grande do Sul [Porto Alegre] (UFRGS)
%+ Airbus Defence and Space [Taufkirchen]
%A Forlin, Bruno
%A Reinbrecht, Cezar
%A Sepúlveda, Johanna
%< avec comité de lecture
%( IFIP Advances in Information and Communication Technology
%B 27th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC)
%C Cusco, Peru
%Y Carolina Metzler
%Y Pierre-Emmanuel Gaillardon
%Y Giovanni De Micheli
%Y Carlos Silva-Cardenas
%Y Ricardo Reis
%I Springer International Publishing
%3 VLSI-SoC: New Technology Enabler
%V AICT-586
%P 209-233
%8 2019-10-06
%D 2019
%R 10.1007/978-3-030-53273-4_10
%K Network-on-Chip
%K Secure MPSoC
%K Timing side-channel attacks
%Z Computer Science [cs]Conference papers
%X Multi-Processor System-on-Chips (MPSoCs) is a standard platform used in time-critical applications. These platforms usually employ Priority-Preemptive NoCs (PP-NoCs), a widely used real-time on-chip interconnection structure that offers communication predictability. A deep analysis of the PP-NoC parameters and their impact on system security is required. Moreover, countermeasures that can protect the system while guaranteeing the real-time capabilities should be proposed and evaluated. To this end, this paper explores and evaluates the impact of the PP-NoCs parameters on system security; exploits PP-NoCs vulnerabilities and demonstrates for the first time two very powerful attacks; and proposes and integrates three new security countermeasures: RT-blinding, RT-masking, and RT-shielding. Results show that PP-NoCs are vulnerable to attacks and that is possible to uncover victim’s information with high accuracy (up to 96.19%). On the other hand, protection techniques were able to harden the system, effectively and efficiently mitigating the vulnerabilities while maintaining deterministic behavior.
%G English
%Z TC 10
%Z WG 10.5
%2 https://inria.hal.science/hal-03476604/document
%2 https://inria.hal.science/hal-03476604/file/501403_1_En_10_Chapter.pdf
%L hal-03476604
%U https://inria.hal.science/hal-03476604
%~ IFIP
%~ IFIP-AICT
%~ IFIP-TC
%~ IFIP-WG
%~ IFIP-VLSISOC
%~ IFIP-TC10
%~ IFIP-WG10-5
%~ IFIP-AICT-586