%0 Conference Proceedings
%T Process Variability Impact on the SET Response of FinFET Multi-level Design
%+ Universidade Federal do Rio Grande do Sul [Porto Alegre] (UFRGS)
%+ Catholic University of Pelotas (UCPEL)
%+ Universidade Federal de Santa Catarina = Federal University of Santa Catarina [Florianópolis] (UFSC)
%A Brendler, Leonardo, H.
%A Zimpeck, Alexandra, L.
%A Meinhardt, Cristina
%A Reis, Ricardo
%< avec comité de lecture
%( IFIP Advances in Information and Communication Technology
%B 27th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC)
%C Cusco, Peru
%Y Carolina Metzler
%Y Pierre-Emmanuel Gaillardon
%Y Giovanni De Micheli
%Y Carlos Silva-Cardenas
%Y Ricardo Reis
%I Springer International Publishing
%3 VLSI-SoC: New Technology Enabler
%V AICT-586
%P 89-113
%8 2019-10-06
%D 2019
%R 10.1007/978-3-030-53273-4_5
%K FinFET technology
%K Multi-level design
%K Process variability
%K Soft errors
%K Single Event Transient
%Z Computer Science [cs]Conference papers
%X Challenges were introduced in integrated circuits design due to the technology scaling. The evolution of integrated circuits has made them more susceptible to the radiation effects, besides increasing the manufacturing process variability. These challenges can lead to circuits operating outside their specification ranges. Transistor arrangement influences the performance of logic cells; complex logic gates can be used to minimize area, delay and power consumption. However, with the increasing relevance of nanometer challenges, it is necessary also to consider these factors at logic level design. This work explores different transistor arrangements for a set of logic functions at the layout level to evaluate the SET response under the process variability. The process variability is analyzed through the work-function fluctuations of the metal gate. The complex gate and the multi-level of NAND2 topologies, that implement the same function, were designed using the 7 nm FinFET ASAP7 Process Design Kit. Results show that the multi-level topology is more robust to the radiation effects at both ideal fabrication process and considering the process variability impact. The LETth value considering the multi-level topology is on average 55% higher than the values considering the complex topology. Moreover, all the logic functions analyzed independently of the topology are more sensitive to the SETs considering the impact of the process variability.
%G English
%Z TC 10
%Z WG 10.5
%2 https://inria.hal.science/hal-03476601/document
%2 https://inria.hal.science/hal-03476601/file/501403_1_En_5_Chapter.pdf
%L hal-03476601
%U https://inria.hal.science/hal-03476601
%~ IFIP
%~ IFIP-AICT
%~ IFIP-TC
%~ IFIP-WG
%~ IFIP-VLSISOC
%~ IFIP-TC10
%~ IFIP-WG10-5
%~ IFIP-AICT-586