%0 Conference Proceedings
%T On Implementable Timed Automata
%+ Airbus Central Research and Technology [Munich] (Airbus Central R&T)
%+ Albert-Ludwigs-Universität Freiburg
%A Feo-Arenis, Sergio
%A Vujinović, Milan
%A Westphal, Bernd
%Z Part 1: Full Papers
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B 40th International Conference on Formal Techniques for Distributed Objects, Components, and Systems (FORTE)
%C Valletta, Malta
%Y Alexey Gotsman
%Y Ana Sokolova
%I Springer International Publishing
%3 Formal Techniques for Distributed Objects, Components, and Systems
%V LNCS-12136
%P 78-95
%8 2020-06-15
%D 2020
%R 10.1007/978-3-030-50086-3_5
%Z Computer Science [cs]
%Z Computer Science [cs]/Networking and Internet Architecture [cs.NI]Conference papers
%X Generating code from networks of timed automata is a well-researched topic with many proposed approaches, which have in common that they not only generate code for the processes in the network, but necessarily generate additional code for a global scheduler which implements the timed automata semantics. For distributed systems without shared memory, this additional component is, in general, undesired.In this work, we present a new approach to the generation of correct code (without global scheduler) for distributed systems without shared memory yet with (almost) synchronous clocks if the source model does not depend on a global scheduler. We characterise a set of implementable timed automata models and provide a translation to a timed while language. We show that each computation of the generated program has a network computation path with the same observable behaviour.
%G English
%Z TC 6
%Z WG 6.1
%2 https://inria.hal.science/hal-03283229/document
%2 https://inria.hal.science/hal-03283229/file/495615_1_En_5_Chapter.pdf
%L hal-03283229
%U https://inria.hal.science/hal-03283229
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-TC
%~ IFIP-WG
%~ IFIP-TC6
%~ IFIP-WG6-1
%~ IFIP-FORTE
%~ IFIP-LNCS-12136