%0 Conference Proceedings
%T Optics for Disaggregating Data Centers and Disintegrating Computing
%+ Aristotle University of Thessaloniki
%+ Center for Interdisciplinary Research and Innovation (CIRI)
%+ Department of Computer Engineering and Informatics [Patras]
%A Terzenidis, Nikos
%A Moralis-Pegios, Miltiadis
%A Pitris, Stelios
%A Mitsolidou, Charoula
%A Mourgias-Alexandris, George
%A Tsakyridis, Apostolis
%A Vagionas, Christos
%A Vyrsokinos, Konstantinos
%A Alexoudi, Theoni
%A Pleros, Nikos
%Z Part 1: Regular Papers
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B 23th International IFIP Conference on Optical Network Design and Modeling (ONDM)
%C Athens, Greece
%Y Anna Tzanakaki
%Y Manos Varvarigos
%Y Raul Muñoz
%Y Reza Nejabati
%Y Noboru Yoshikane
%Y Markos Anastasopoulos
%Y Johann Marquez-Barja
%I Springer International Publishing
%3 Optical Network Design and Modeling
%V LNCS-11616
%P 274-285
%8 2019-05-13
%D 2019
%R 10.1007/978-3-030-38085-4_24
%K Computing architectures
%K Disintegrated computing
%K Network-on-Chip
%K Silicon photonics
%Z Computer Science [cs]
%Z Computer Science [cs]/Networking and Internet Architecture [cs.NI]Conference papers
%X We present a review of photonic Network-on-Chip (pNoC) architectures and experimental demonstrations, concluding to the main obstacles that still impede the materialization of these concepts. We also propose the employment of optics in chip-to-chip (C2C) computing architectures rather than on-chip layouts towards reaping their benefits while avoiding technology limitations on the way to many-core set-ups. We identify multisocket boards as the most prominent application area and present recent advances in optically enabled multisocket boards, revealing successful 40 Gb/s transceiver and routing capabilities via integrated photonics. These results indicate the potential to bring energy consumption down by more than 60% compared to current QuickPath Interconnect (QPI) protocol, while turning multisocket architectures into a single-hop low-latency setup for even more than 4 interconnected sockets, which form currently the electronic baseline.
%G English
%Z TC 6
%Z WG 6.10
%2 https://inria.hal.science/hal-03200687/document
%2 https://inria.hal.science/hal-03200687/file/484327_1_En_24_Chapter.pdf
%L hal-03200687
%U https://inria.hal.science/hal-03200687
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-TC
%~ IFIP-WG
%~ IFIP-TC6
%~ IFIP-LNCS-11616
%~ IFIP-ONDM
%~ IFIP-WG6-10