%0 Conference Proceedings
%T Dual-Layer Locality-Aware Optical Interconnection Architecture for Latency-Critical Resource Disaggregation Environments
%+ Aristotle University of Thessaloniki
%+ Center for Interdisciplinary Research and Innovation (CIRI)
%A Terzenidis, Nikos
%A Moralis-Pegios, Miltiadis
%A Alexoudi, Theoni
%A Pitris, Stelios
%A Vyrsokinos, Konstantinos
%A Pleros, Nikos
%Z Part 1: Regular Papers
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B 23th International IFIP Conference on Optical Network Design and Modeling (ONDM)
%C Athens, Greece
%Y Anna Tzanakaki
%Y Manos Varvarigos
%Y Raul Muñoz
%Y Reza Nejabati
%Y Noboru Yoshikane
%Y Markos Anastasopoulos
%Y Johann Marquez-Barja
%I Springer International Publishing
%3 Optical Network Design and Modeling
%V LNCS-11616
%P 299-309
%8 2019-05-13
%D 2019
%R 10.1007/978-3-030-38085-4_26
%K Silicon-photonics
%K Optical switch
%K Interconnection architecture
%K Disaggregated data center
%K Traffic locality
%Z Computer Science [cs]
%Z Computer Science [cs]/Networking and Internet Architecture [cs.NI]Conference papers
%X Significant research efforts, both industrial and academic, have been committed in the direction of Rack-scale computing through resource disaggregation, that aims to increase resource utilization at a reduced energy and cost envelope. However, the realization of resource disaggregation necessitates an underlying network infrastructure that can compete with a challenging set of requirements including low-latency performance and high-port count connectivity, as well as high data-rate operation. At the same time, it is crucial for the interconnection architecture to be able to accommodate efficient delivery of traffic with different locality characteristics. We propose a dual-layer locality-aware optical interconnection architecture for disaggregated Data Centers by combining the STREAMS silicon-based on-board communication paradigm with the disaggregation-oriented Hipoλaos high-port count switch. Simulation evaluation of a 256-node disaggregated system, comprising 32 optically-interconnected 8-socket boards, revealed up to 100% throughput and mean, p99 latencies not higher than 335 nsec and 610 nsec, respectively, when a 50:50 ratio between on- and off-board traffic is employed. Evaluation of the same layout with 75:25 on-/off-board traffic yields even lower mean and p99 latency at 210 ns and 553 ns, respectively.
%G English
%Z TC 6
%Z WG 6.10
%2 https://inria.hal.science/hal-03200656/document
%2 https://inria.hal.science/hal-03200656/file/484327_1_En_26_Chapter.pdf
%L hal-03200656
%U https://inria.hal.science/hal-03200656
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-TC
%~ IFIP-WG
%~ IFIP-TC6
%~ IFIP-LNCS-11616
%~ IFIP-ONDM
%~ IFIP-WG6-10