%0 Conference Proceedings
%T Design of a Real-Time DSP Engine on RF-SoC FPGA for 5G Networks
%+ National and Kapodistrian University of Athens (NKUA)
%+ National Technical University of Athens [Athens] (NTUA)
%A Kitsakis, Vasileios
%A Kanta, Konstantina
%A Stratakos, Ioannis
%A Giannoulis, Giannis
%A Apostolopoulos, Dimitrios
%A Lentaris, George
%A Avramopoulos, Hercules
%A Soudris, Dimitrios
%A Reisis, Dionysios, I.
%Z Part 2: Poster Papers
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B 23th International IFIP Conference on Optical Network Design and Modeling (ONDM)
%C Athens, Greece
%Y Anna Tzanakaki
%Y Manos Varvarigos
%Y Raul Muñoz
%Y Reza Nejabati
%Y Noboru Yoshikane
%Y Markos Anastasopoulos
%Y Johann Marquez-Barja
%I Springer International Publishing
%3 Optical Network Design and Modeling
%V LNCS-11616
%P 540-551
%8 2019-05-13
%D 2019
%R 10.1007/978-3-030-38085-4_46
%K 5G Networks
%K 5G-PHOS
%K DSP engine
%K FPGA
%Z Computer Science [cs]
%Z Computer Science [cs]/Networking and Internet Architecture [cs.NI]Conference papers
%X 5G advances the wireless communications by providing a significant improvement to the data rate, capability of connected devices and data volumes compared to the previous generations. While these advantages combine along with a wider range of applications to merit the end-user, the technologies to be used are not specified. Considering this problem and in order to efficiently support the 5G deployment researchers and engineers turned their attention on FPGA base band architectures that keep the implementation cost relatively low and at the same time they are reprogramable to provide solutions to the emerging requirements and their consequent modifications. Aiming at the contribution to the 5G technologies the current paper introduces the design of a base band DSP architecture that targets the required real time performance. Moreover, the proposed architecture is scalable by efficiently parallelizing and/or pipelining the corresponding data paths. The paper presents the pilot FPGA designs of the IFFT/FFT and Sampling Frequency Offset (SFO) functions that achieve a 500 Msps performance on a RF-SoC Xilinx ZCU111 board.
%G English
%Z TC 6
%Z WG 6.10
%2 https://inria.hal.science/hal-03200640/document
%2 https://inria.hal.science/hal-03200640/file/484327_1_En_46_Chapter.pdf
%L hal-03200640
%U https://inria.hal.science/hal-03200640
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-TC
%~ IFIP-WG
%~ IFIP-TC6
%~ IFIP-LNCS-11616
%~ IFIP-ONDM
%~ IFIP-WG6-10