%0 Conference Proceedings
%T Mapping Spiking Neural Networks on Multi-core Neuromorphic Platforms: Problem Formulation and Performance Analysis
%+ Dipartimento di Automatica e Informatica [Torino] (DAUIN)
%A Barchi, Francesco
%A Urgese, Gianvito
%A Macii, Enrico
%A Acquaviva, Andrea
%< avec comité de lecture
%( IFIP Advances in Information and Communication Technology
%B 26th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC)
%C Verona, Italy
%Y Nicola Bombieri
%Y Graziano Pravadelli
%Y Masahiro Fujita
%Y Todd Austin
%Y Ricardo Reis
%I Springer International Publishing
%3 VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms
%V AICT-561
%P 167-186
%8 2018-10-08
%D 2018
%R 10.1007/978-3-030-23425-6_9
%K Graph mapping
%K Multicore neuromorphic architectures
%K Spiking neural networks
%Z Computer Science [cs]Conference papers
%X In this paper, we propose a methodology for efficiently mapping concurrent applications over a globally asynchronous locally synchronous (GALS) multi-core architecture designed for simulating a Spiking Neural Network (SNN) in real-time. The problem of neuron-to-core mapping is relevant as a non-efficient allocation may impact real-time and reliability of the SNN execution. We designed a task placement pipeline capable of analysing the network of neurons and producing a placement configuration that enables a reduction of communication between computational nodes. We compared four Placement techniques by evaluating the overall post-placement synaptic elongation that represents the cumulative distance that spikes generated by neurons running on a core have to travel to reach their destination core. Results point out that mapping solutions taking into account the directionality of the SNN application provide a better placement configuration.
%G English
%Z TC 10
%Z WG 10.5
%2 https://inria.hal.science/hal-02321774/document
%2 https://inria.hal.science/hal-02321774/file/485996_1_En_9_Chapter.pdf
%L hal-02321774
%U https://inria.hal.science/hal-02321774
%~ IFIP
%~ IFIP-AICT
%~ IFIP-TC
%~ IFIP-WG
%~ IFIP-VLSISOC
%~ IFIP-TC10
%~ IFIP-WG10-5
%~ IFIP-AICT-561