%0 Conference Proceedings
%T Improved Test Solutions for COTS-Based Systems in Space Applications
%+ Politecnico di Torino = Polytechnic of Turin (Polito)
%+ German Aerospace Center (DLR)
%A Cantoro, Riccardo
%A Carbonara, Sara
%A Florida, Andrea
%A Sanchez, Ernesto
%A Sonza Reorda, Matteo
%A Mess, Jan-Gerd
%< avec comité de lecture
%( IFIP Advances in Information and Communication Technology
%B 26th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC)
%C Verona, Italy
%Y Nicola Bombieri
%Y Graziano Pravadelli
%Y Masahiro Fujita
%Y Todd Austin
%Y Ricardo Reis
%I Springer International Publishing
%3 VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms
%V AICT-561
%P 187-206
%8 2018-10-08
%D 2018
%R 10.1007/978-3-030-23425-6_10
%Z Computer Science [cs]Conference papers
%X In order to widen the spectrum of available products, companies involved in space electronics are exploring the possible adoption of COTS components instead of space-qualified ones. However, the adoption of COTS devices and boards requires suitable solutions able to guarantee the same level of dependability. A mix of different solutions can be considered for this purpose. Test techniques play a major role, since they must guarantee that a high percentage of permanent faults can be detected (both at the end of the manufacturing and during the mission) while matching several constraints in terms of system accessibility and hardware complexity. In this paper we focus on the test of the electronics used within launchers, and outline an approach based on Software-based Self-test. The proposed solutions are currently being adopted within the MaMMoTH-Up project, targeting the development of an innovative COTS-based system to be used on the Ariane5 launcher. The approach aims at testing both the OR1200 processor and the different peripheral modules adopted in the system, while providing new techniques for the identification of safe faults. The results show the effectiveness and current limitations of the method, also including a comparison between functional and structural test approaches.
%G English
%Z TC 10
%Z WG 10.5
%2 https://inria.hal.science/hal-02321761/document
%2 https://inria.hal.science/hal-02321761/file/485996_1_En_10_Chapter.pdf
%L hal-02321761
%U https://inria.hal.science/hal-02321761
%~ IFIP
%~ IFIP-AICT
%~ IFIP-TC
%~ IFIP-WG
%~ IFIP-VLSISOC
%~ IFIP-TC10
%~ IFIP-WG10-5
%~ IFIP-AICT-561