%0 Conference Proceedings
%T Evaluating the Impact of Resistive Defects on FinFET-Based SRAMs
%+ Universidade Federal do Rio Grande do Sul [Porto Alegre] (UFRGS)
%+ Pontifícia Universidade Católica do Rio Grande do Sul [Brasil] = Pontifical Catholic University of Rio Grande do Sul [Brazil] = Université catholique pontificale de Rio Grande do Sul [Brésil] (PUC-RS)
%A Copetti, Thiago, S.
%A Medeiros, Guilherme, C.
%A Poehls, Letícia
%A Balen, Tiago, R.
%< avec comité de lecture
%( IFIP Advances in Information and Communication Technology
%B 25th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC)
%C Abu Dhabi, United Arab Emirates
%Y Michail Maniatakos
%Y Ibrahim (Abe) M. Elfadel
%Y Matteo Sonza Reorda
%Y H. Fatih Ugurdag
%Y José Monteiro
%Y Ricardo Reis
%I Springer International Publishing
%3 VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things
%V AICT-500
%P 22-45
%8 2017-10-23
%D 2017
%R 10.1007/978-3-030-15663-3_2
%K FinFET
%K SRAM
%K Resistive defects
%K SPICE
%K PTM
%Z Computer Science [cs]Conference papers
%X The development of FinFET technology has made possible the continuous scaling-down of CMOS technological nodes. In parallel, the increasing need to store more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy great part of Systems-on-Chip (SoCs). The manufacturing process variation has introduced several types of defects that directly affect the SRAM’s reliability, causing different faults. Thus, it remains unknown if the fault models used in CMOS memory circuits are sufficiently accurate to represent the faulty behavior of FinFET-based memories. In this context, a study of manufacturing’s functional implications regarding resistive defects in FinFET-based SRAMs is presented. In more detail, a complete analysis of static and dynamic fault behavior for FinFET-based SRAMs is described. The proposed analysis has been performed through SPICE simulations, adopting a compact Predictive Technology Model (PTM) of FinFET transistors, considering different technological nodes. Faults have been categorized as single or coupling, static or dynamic.
%G English
%Z TC 10
%Z WG 10.5
%2 https://inria.hal.science/hal-02319796/document
%2 https://inria.hal.science/hal-02319796/file/479099_1_En_2_Chapter.pdf
%L hal-02319796
%U https://inria.hal.science/hal-02319796
%~ IFIP
%~ IFIP-AICT
%~ IFIP-TC
%~ IFIP-WG
%~ IFIP-VLSISOC
%~ IFIP-TC10
%~ IFIP-WG10-5
%~ IFIP-AICT-500