%0 Conference Proceedings
%T Generic Architecture for Lightweight Block Ciphers: A First Step Towards Agile Implementation of Multiple Ciphers
%+ Laboratoire Traitement et Communication de l'Information (LTCI)
%+ Département Communications & Electronique (COMELEC)
%+ Secure and Safe Hardware (SSH)
%A Tehrani, Etienne
%A Danger, Jean-Luc
%A Graba, Tarik
%Z Chaire « Connected Cars & Cyber Security » (C3S)
%Z Part 2: Real World
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B 12th IFIP International Conference on Information Security Theory and Practice (WISTP)
%C Brussels, Belgium
%Y Olivier Blazy
%Y Chan Yeob Yeun
%I Springer International Publishing
%3 Information Security Theory and Practice
%V LNCS-11469
%P 28-43
%8 2018-12-10
%D 2018
%R 10.1007/978-3-030-20074-9_4
%K Lightweight cryptography
%K SPN
%K ASIC
%K Configurable architecture
%Z Computer Science [cs]
%Z Computer Science [cs]/Hardware Architecture [cs.AR]
%Z Computer Science [cs]/Computer Arithmetic
%Z Computer Science [cs]/Cryptography and Security [cs.CR]
%Z Computer Science [cs]/Digital Libraries [cs.DL]
%Z Computer Science [cs]/Modeling and Simulation
%Z Engineering Sciences [physics]/ElectronicsConference papers
%X Lightweight cryptography is at the heart of today’s security needs for embedded systems. The standardised cryptographic algorithms, such as the Advanced Encryption Standard (AES), hardly fits the resource restrictions of those small and pervasive devices. From this observation a plethora of Lightweight Block Ciphers have been proposed. Every algorithm has its own advantages in terms of security, complexity, latency, performances. This paper presents first a classification of some popular Substitution-Permutation-Networks (SPN) class of lightweight ciphers according to their architecture and features which share many common operators. From this last point, we studied a round-based generic hardware architecture that allows a security architect to dynamically change the lightweight cryptographic algorithms to be executed. The results of the ASIC implementation show that the configuration part of the proposed flexible architecture adds significant complexity. If compared with the parallel implementation of several algorithms, the complexity ratio becomes interesting when the number of algorithms (or the level of agility) increases. For instance, if we consider 6 SPN ciphers, the configurable architecture provides a complexity reduction of 62.5%, whereas there is no reduction with 4 algorithms.
%G English
%Z TC 11
%Z WG 11.2
%2 https://hal.science/hal-02294599/document
%2 https://hal.science/hal-02294599/file/484602_1_En_4_Chapter.pdf
%L hal-02294599
%U https://hal.science/hal-02294599
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%~ IFIP-TC11
%~ TDS-MACS
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