%0 Conference Proceedings
%T DLIR: An Intermediate Representation for Deep Learning Processors
%+ CAS Institute of Computing Technology (ICT)
%+ University of Chinese Academy of Sciences [Beijing] (UCAS)
%+ Cambricon Technologies
%A Lan, Huiying
%A Du, Zidong
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B 15th IFIP International Conference on Network and Parallel Computing (NPC)
%C Muroran, Japan
%Y Feng Zhang
%Y Jidong Zhai
%Y Marc Snir
%Y Hai Jin
%Y Hironori Kasahara
%Y Mateo Valero
%I Springer International Publishing
%3 Network and Parallel Computing
%V LNCS-11276
%P 169-173
%8 2018-11-29
%D 2018
%R 10.1007/978-3-030-05677-3_19
%K Deep learning processor
%K Intermediate representation
%K Deep learning framework
%K Deep learning
%Z Computer Science [cs]Conference papers
%X The Deep learning processor (DLP), especially ASIC-based accelerators, have been proved to be a promising device for accelerating the computation of deep learning algorithms. However, the learning cost of mastering these DLPs is high as they use different programming interfaces. On the other hand, many deep learning frameworks are proposed to ease the burden of developing deep learning algorithms, but few of them support DLPs. Due to the special features in DLPs, it is hard to integrate a DLP into existed frameworks.In this paper, we propose an intermediate representation (called DLIR) to bridge the gap between DL frameworks and DLPs. DLIR is a tensor-based language with built-in tensor intrinsics that can be directly mapped to hardware primitives. We show that DLIR allows better developing efficiency and is able to generate efficient code.
%G English
%Z TC 10
%Z WG 10.3
%2 https://inria.hal.science/hal-02279553/document
%2 https://inria.hal.science/hal-02279553/file/477597_1_En_19_Chapter.pdf
%L hal-02279553
%U https://inria.hal.science/hal-02279553
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-TC
%~ IFIP-TC10
%~ IFIP-NPC
%~ IFIP-WG10-3
%~ IFIP-LNCS-11276