%0 Conference Proceedings
%T Systolic Array Based Accelerator and Algorithm Mapping for Deep Learning Algorithms
%+ College of Computer Science [Changsha]
%A Yang, Zhijie
%A Wang, Lei
%A Ding, Dong
%A Zhang, Xiangyu
%A Deng, Yu
%A Li, Shiming
%A Dou, Qiang
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B 15th IFIP International Conference on Network and Parallel Computing (NPC)
%C Muroran, Japan
%Y Feng Zhang
%Y Jidong Zhai
%Y Marc Snir
%Y Hai Jin
%Y Hironori Kasahara
%Y Mateo Valero
%I Springer International Publishing
%3 Network and Parallel Computing
%V LNCS-11276
%P 153-158
%8 2018-11-29
%D 2018
%R 10.1007/978-3-030-05677-3_16
%K Accelerator
%K Systolic array
%K DNN
%K Data mapping
%Z Computer Science [cs]Conference papers
%X As the depth of DNN increases, the need for DNN calculations for the storage and computing power of the underlying computing platform is increasing. In this work, we implement an accelerator on FPGA for deep learning algorithms (CNN and RNN). The core computing module of the accelerator is a 32 * 32 systolic array of PEs. A mapping method for variable size of CNN and RNN algorithms is proposed. The experiment result shows that the maximum power consumption of the accelerator is 7.5W@100Mhz, the peak performance is 0.2Tops/s, and the real performance is 7.6Mops@100Mhz when running the 1st layer of LeNet-5.
%G English
%Z TC 10
%Z WG 10.3
%2 https://inria.hal.science/hal-02279547/document
%2 https://inria.hal.science/hal-02279547/file/477597_1_En_16_Chapter.pdf
%L hal-02279547
%U https://inria.hal.science/hal-02279547
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-TC
%~ IFIP-TC10
%~ IFIP-NPC
%~ IFIP-WG10-3
%~ IFIP-LNCS-11276