%0 Conference Proceedings
%T An Efficient Polarity Optimization Approach for Fixed Polarity Reed-Muller Logic Circuits Based on Novel Binary Differential Evolution Algorithm
%+ Beihang University (BUAA)
%+ Space Star technology CO., Ltd
%+ Institute of Computing Technology [Beijing] (ICT)
%A He, Zhenxue
%A Qin, Guangjun
%A Xiao, Limin
%A Gu, Fei
%A Huo, Zhisheng
%A Ruan, Li
%A Wang, Haitao
%A Zhang, Longbing
%A Liu, Jianbin
%A Liu, Shaobo
%A Wang, Xiang
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B 14th IFIP International Conference on Network and Parallel Computing (NPC)
%C Hefei, China
%Y Xuanhua Shi
%Y Hong An
%Y Chao Wang
%Y Mahmut Kandemir
%Y Hai Jin
%I Springer International Publishing
%3 Network and Parallel Computing
%V LNCS-10578
%P 118-121
%8 2017-10-20
%D 2017
%R 10.1007/978-3-319-68210-5_11
%Z Computer Science [cs]Conference papers
%X The bottleneck of integrated circuit design could potentially be alleviated by using Reed-Muller (RM) logic circuits due to their remarkable superiority in power, area and testability. In this paper, we propose a Novel Binary Differential Evolution (DE) algorithm (NBDE) to solve the discrete binary-encoded combination optimization problem. Moreover, based on the NBDE, we propose an Efficient Polarity Optimization Approach (EPOA) for Fixed Polarity RM (FPRM) logic circuits, which uses the NBDE to search the best polarity under a performance constraint. To the best of our knowledge, we are the first to use DE to optimize RM circuits. The experimental results on 24 MCNC benchmark circuits show the effectiveness and superiority of EPOA.
%G English
%Z TC 10
%Z WG 10.3
%2 https://inria.hal.science/hal-01705436/document
%2 https://inria.hal.science/hal-01705436/file/457609_1_En_11_Chapter.pdf
%L hal-01705436
%U https://inria.hal.science/hal-01705436
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-TC
%~ IFIP-TC10
%~ IFIP-NPC
%~ IFIP-WG10-3
%~ IFIP-LNCS-10578