%0 Conference Proceedings
%T A 20 Gb/s Wireline Receiver with Adaptive CTLE and Half-Rate DFE in 0.13 µm Technology
%+ Southeast University [Jiangsu]
%A Zhang, Yinhang
%A Hu, Qingsheng
%A Zhan, Yongzheng
%Z Part 6: Circuit Design
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B 15th International Conference on Wired/Wireless Internet Communication (WWIC)
%C St. Petersburg, Russia
%Y Yevgeni Koucheryavy
%Y Lefteris Mamatas
%Y Ibrahim Matta
%Y Aleksandr Ometov
%Y Panagiotis Papadimitriou
%I Springer International Publishing
%3 Wired/Wireless Internet Communications
%V LNCS-10372
%P 292-303
%8 2017-06-21
%D 2017
%R 10.1007/978-3-319-61382-6_24
%K CTLE
%K DFE
%K Serial link
%K Design complexity
%Z Computer Science [cs]
%Z Computer Science [cs]/Networking and Internet Architecture [cs.NI]Conference papers
%X This paper presents a 20 Gb/s receive equalizer including an adaptive continuous time linear equalizer (CTLE) and a 2-tap half-rate decision feedback equalizer (DFE) in 0.13 µm BiCMOS technology for high speed serial link. The CTLE can adjust the ratio of high frequency and low frequency components adaptively by detecting the energy at both ends of a slicer and then generating a control signal by an integrator. Following the CTLE is a half-rate DFE which can get a better trade-off between the working speed and design complexity especially for the case of 20 Gb/s or above. The chip area including pads and chip guarding is about 0.72 × 0.86 mm2 and the power consumption is about 528 mW. Post simulation results show that the horizontal eye opening of the equalized data can be up to 0.9 UI at 20 Gb/s.
%G English
%Z TC 6
%Z WG 6.2
%2 https://inria.hal.science/hal-01675415/document
%2 https://inria.hal.science/hal-01675415/file/453598_1_En_24_Chapter.pdf
%L hal-01675415
%U https://inria.hal.science/hal-01675415
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-TC
%~ IFIP-TC6
%~ IFIP-WG6-2
%~ IFIP-WWIC
%~ IFIP-LNCS-10372