%0 Conference Proceedings
%T Memory-Side Acceleration for XML Parsing
%+ Beijing Institute of Technology (BIT)
%+ Microsoft Research [Cambridge] (Microsoft)
%+ Florida International University [Miami] (FIU)
%+ University of California [Davis] (UC Davis)
%A Tang, Jie
%A Liu, Shaoshan
%A Gu, Zhimin
%A Liu, Chen
%A Gaudiot, Jean-Luc
%Z Part 7: Session 7: Best Paper – 2
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B 8th Network and Parallel Computing (NPC)
%C Changsha,, China
%Y Erik Altman
%Y Weisong Shi
%I Springer
%3 Network and Parallel Computing
%V LNCS-6985
%P 277-292
%8 2011-10-21
%D 2011
%R 10.1007/978-3-642-24403-2_22
%Z Computer Science [cs]Conference papers
%X As Extensible Markup Language (XML) becomes prevalent in cloud computing environments, it also introduces significant performance overheads. In this paper, we analyze the performance of XML parsing, identify that a significant fraction of the performance overhead is indeed incurred by memory data loading. To address this problem, we propose implementing memory-side acceleration on top of computation-side acceleration of XML parsing. To this end, we study the impact of memory-side acceleration on performance, and evaluate its implementation feasibility including bus bandwidth utilization, hardware cost, and energy consumption. Our results show that this technique is able to improve performance by up to 20% as well as produce up to 12.77% of energy saving when implemented in 32 nm technology.
%G English
%Z TC 10
%Z WG 10.3
%2 https://inria.hal.science/hal-01593022/document
%2 https://inria.hal.science/hal-01593022/file/978-3-642-24403-2_22_Chapter.pdf
%L hal-01593022
%U https://inria.hal.science/hal-01593022
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-AICT
%~ IFIP-TC
%~ IFIP-TC10
%~ IFIP-NPC
%~ IFIP-WG10-3
%~ IFIP-LNCS-6985