@inproceedings{gu:hal-01593019,
  TITLE = {{An Efficient Architectural Design of Hardware Interface for Heterogeneous Multi-core System}},
  AUTHOR = {Gu, Xiongli and Yang, Jie and Wu, Xiamin and Huang, Chunming and Liu, Peng},
  URL = {https://inria.hal.science/hal-01593019},
  NOTE = {Part 8: Session 8: Microarchitecture},
  BOOKTITLE = {{8th Network and Parallel Computing (NPC)}},
  ADDRESS = {Changsha,, China},
  EDITOR = {Erik Altman and Weisong Shi},
  PUBLISHER = {{Springer}},
  SERIES = {Network and Parallel Computing},
  VOLUME = {LNCS-6985},
  PAGES = {313-323},
  YEAR = {2011},
  MONTH = Oct,
  DOI = {10.1007/978-3-642-24403-2\_24},
  KEYWORDS = {data flow graph (DFG) ; multi-core system ; parallel programming},
  PDF = {https://inria.hal.science/hal-01593019/file/978-3-642-24403-2_24_Chapter.pdf},
  HAL_ID = {hal-01593019},
  HAL_VERSION = {v1},
}