%0 Conference Proceedings
%T A SAR Pipeline ADC Embedding Time Interleaved DAC Sharing for Ultra-low Power Camera Front Ends
%+ School of Electrical and Computer Engineering
%A Amaravati, Anvesha
%A Chugh, Manan
%A Raychowdhury, Arijit
%< avec comité de lecture
%( IFIP Advances in Information and Communication Technology
%B 23th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC)
%C Daejeon, South Korea
%3 VLSI-SoC: Design for Reliability, Security, and Low Power
%V AICT-483
%P 131-149
%8 2015-10-05
%D 2015
%R 10.1007/978-3-319-46097-0_7
%Z Computer Science [cs]Conference papers
%X The growing need for ultra-low power cameras for sensors, surveillance and consumer applications has resulted in significant advances in compressed domain data acquisition from pixel arrays. In this journal we present a novel 64-input Successive Approximation (SAR) Pipeline analog-to-digital converter (ADC) suitable for compressed domain data acquisition in camera front-ends. The proposed architecture features a time interleaved capacitive digital-to-analog converter (DAC) shared between column parallel ADCs for area savings (2.28X); and a shared amplifier stage for power savings (60 %), achieving 4X throughput as compared to traditional architectures. Simulations on a 130 nm foundry process shows that the proposed SAR Pipeline ADC draws 31 $$\upmu $$W at 2 MS/s having a target Figure-of-Merit (FOM) of 87 fJ/conv. per step at Nyquist rate. The proposed compressive sensing front end achieves per patch energy per patch of 0.9 nJ.
%G English
%Z TC 10
%Z WG 10.5
%2 https://inria.hal.science/hal-01578616/document
%2 https://inria.hal.science/hal-01578616/file/431455_1_En_7_Chapter.pdf
%L hal-01578616
%U https://inria.hal.science/hal-01578616
%~ IFIP
%~ IFIP-AICT
%~ IFIP-TC
%~ IFIP-WG
%~ IFIP-VLSISOC
%~ IFIP-TC10
%~ IFIP-WG10-5
%~ IFIP-AICT-483