%0 Conference Proceedings
%T Information Leakage Discovery Techniques to Enhance Secure Chip Design
%+ Politecnico di Milano [Milan] (POLIMI)
%+ Università degli Studi di Bergamo = University of Bergamo (UniBg)
%+ STMicroelectronics
%A Barenghi, Alessandro
%A Pelosi, Gerardo
%A Teglia, Yannick
%Z Part 4: Algorithms
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B 5th Workshop on Information Security Theory and Practices (WISTP)
%C Heraklion, Crete, Greece
%Y Claudio A. Ardagna
%Y Jianying Zhou
%I Springer
%3 Information Security Theory and Practice. Security and Privacy of Mobile Devices in Wireless Communication
%V LNCS-6633
%P 128-143
%8 2011-06-01
%D 2011
%R 10.1007/978-3-642-21040-2_9
%K Side-Channel Attacks
%K Embedded Systems Security
%K Differential Power Attacks
%K Differential Electromagnetic Attacks
%Z Computer Science [cs]Conference papers
%X Side channel attacks analyzing both power consumption and electromagnetic (EM) radiations are a well known threat to the security of devices dealing with sensitive data. Whilst it is well known that the EM emissions of a chip represent an information leakage stronger than the overall dynamic power consumption, the actual relation between the emissions and the computations is still a subject under exploration. It is important for the chip designer to be able to distinguish which portions of the measured EM emissions are actually correlated with the sensitive information. Our technique obtains a detailed profile of the information leakage, identifying which harmonic components carry the largest part of the it on the measured signals. It may be successfully integrated in a design workflow as a post-testing feedback from the prototype chip, in the form of additional constraints aimed at reducing the local wires congestion up to a point where the emissions are no longer sufficient to conduct an attack. The analysis allows the design of ad-hoc countermeasures (shields and/or EM jammers), which do not require architectural changes to the chip. We provide a validation of the proposed technique on a commercial grade ARM Cortex-M3 based System on Chip (SoC), executing a software implementation of AES-128. The proposed approach is more efficient than a search of the whole frequency spectrum, allowing to conduct a deeper analysis with the same timing constraints.
%G English
%Z TC 11
%Z WG 11.2
%2 https://inria.hal.science/hal-01573297/document
%2 https://inria.hal.science/hal-01573297/file/978-3-642-21040-2_9_Chapter.pdf
%L hal-01573297
%U https://inria.hal.science/hal-01573297
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-TC
%~ IFIP-TC11
%~ IFIP-WISTP
%~ IFIP-WG11-2
%~ IFIP-LNCS-6633