%0 Conference Proceedings
%T Unifying Thread-Level Speculation and Transactional Memory
%+ Technical University of Lisbon
%+ Ecole Polytechnique Fédérale de Lausanne (EPFL)
%A Barreto, João
%A Dragojevic, Aleksandar
%A Ferreira, Paulo
%A Filipe, Ricardo
%A Guerraoui, Rachid
%Z Part 3: Architecture and Performance
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B 13th International Middleware Conference (MIDDLEWARE)
%C Montreal, QC, Canada
%Y Priya Narasimhan
%Y Peter Triantafillou
%I Springer
%3 Middleware 2012
%V LNCS-7662
%P 187-207
%8 2012-12-03
%D 2012
%R 10.1007/978-3-642-35170-9_10
%Z Computer Science [cs]
%Z Computer Science [cs]/Networking and Internet Architecture [cs.NI]Conference papers
%X The motivation of this work is to ask whether Transactional Memory (TM) and Thread-Level Speculation (TLS), two prominent concurrency paradigms usually considered separately, can be combined into a hybrid approach that extracts untapped parallelism and speed-up from common programs.We show that the answer is positive by describing an algorithm, called TLSTM, that leverages an existing TM with TLS capabilities. We also show that our approach is able to achieve up to a 48% increase in throughput over the base TM, on read dominated workloads of long transactions in a multi-threaded application, among other results.
%G English
%Z TC 6
%Z WG 6.1
%2 https://inria.hal.science/hal-01555545/document
%2 https://inria.hal.science/hal-01555545/file/978-3-642-35170-9_10_Chapter.pdf
%L hal-01555545
%U https://inria.hal.science/hal-01555545
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-TC
%~ IFIP-WG
%~ IFIP-TC6
%~ IFIP-WG6-1
%~ IFIP-MIDDLEWARE
%~ IFIP-LNCS-7662