%0 Conference Proceedings
%T An Elastic Architecture Adaptable to Millions of Application Scenarios
%+ Chinese Academy of Sciences [Beijing] (CAS)
%+ Loongson Technologies Corporation Limited [Beijing]
%A Chen, Yunji
%A Chen, Tianshi
%A Guo, Qi
%A Xu, Zhiwei
%A Zhang, Lei
%Z Part 5: Performance Modeling, Prediction, and Tuning
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B 9th International Conference on Network and Parallel Computing (NPC)
%C Gwangju, South Korea
%Y James J. Park
%Y Albert Zomaya
%Y Sang-Soo Yeo
%Y Sartaj Sahni
%I Springer
%3 Network and Parallel Computing
%V LNCS-7513
%P 188-195
%8 2012-09-06
%D 2012
%R 10.1007/978-3-642-35606-3_22
%Z Computer Science [cs]Conference papers
%X With the rapid development of computer industry, the number of applications has been growing rapidly. Furthermore, even one application may correspond to different application scenarios which impose different requirements on performance or power. This trend raises the following question: how to design processors that best suit millions of application scenarios? It is impractical to design a dedicated processor for each single application scenario. A better alternative is to design a general-purpose processor architecture that can generate different architecture instances on demand. This paper proposes a novel CPU architecture called Elastic Architecture (EA), which can be dynamically configured into different architecture instances to suit different application scenarios. By employing reconfigurable architecture components (instruction set, branch predictor, data path, memory hierarchy, concurrency, status & control, and so on), the EA can achieve considerable elasticities on each application, which enables the EA to meet the performance or power requirements associated with each application scenario. We validate the effectiveness of the EA on a prototype implementation called Sim-EA. We demonstrate that Sim-EA exhibits large elasticities over 26 benchmarks of SPEC CPU2000, enabling Sim-EA to reduce the average energy-delay product (EDP) by 31.14% of a fixed baseline architecture.
%G English
%Z TC 10
%Z WG 10.3
%2 https://inria.hal.science/hal-01551328/document
%2 https://inria.hal.science/hal-01551328/file/978-3-642-35606-3_22_Chapter.pdf
%L hal-01551328
%U https://inria.hal.science/hal-01551328
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-AICT
%~ IFIP-TC
%~ IFIP-TC10
%~ IFIP-NPC
%~ IFIP-WG10-3
%~ IFIP-LNCS-7513