%0 Conference Proceedings
%T Design of a Reliable XOR-XNOR Circuit for Arithmetic Logic Units
%+ Université de Monastir - University of Monastir (UM)
%+ University of Turku
%+ Xi'an Jiaotong-Liverpool University [Suzhou]
%A Karmani, Mouna
%A Khedhiri, Chiraz
%A Hamdi, Belgacem
%A Rahmani, Amir-Mohammad
%A Man, Ka, Lok
%A Wan, Kaiyu
%Z Part 12: DATICS
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B 9th International Conference on Network and Parallel Computing (NPC)
%C Gwangju, South Korea
%Y James J. Park
%Y Albert Zomaya
%Y Sang-Soo Yeo
%Y Sartaj Sahni
%I Springer
%3 Network and Parallel Computing
%V LNCS-7513
%P 516-523
%8 2012-09-06
%D 2012
%R 10.1007/978-3-642-35606-3_61
%K XOR-XNOR circuits
%K Concurrent Error Detection
%K fault-secure property
%K self-testing property
%K fault model
%Z Computer Science [cs]Conference papers
%X Computer systems used in safety-critical applications like space, avionic and biomedical applications require high reliable integrated circuits (ICs) to ensure the accuracy of data they process. As Arithmetic Logic Units (ALUs) are essential element of computers, designing reliable ALUs is becoming an appropriate strategy to design fault-tolerant computers. In fact, with the continuous increase of integration densities and complexities ICs are susceptible to many modes of failure. Thereby, Reliable operation of ALUs is critical for high performance safety-critical computers. Given that XOR-XNOR circuits are basic building blocks in ALUs, designing efficient reliable XOR-XNOR gates is an important challenge in the area of high performance computers. The reliability enhancement technique presented in this work is based on using a Concurrent Error Detection (CED) based reliable XOR-XNOR circuit implementation to detect permanent and transient faults in ALUs during normal operation in order to improve the reliability of highly critical computer systems. The proposed design is performed using the 32 nm process technology.
%G English
%Z TC 10
%Z WG 10.3
%2 https://inria.hal.science/hal-01551326/document
%2 https://inria.hal.science/hal-01551326/file/978-3-642-35606-3_61_Chapter.pdf
%L hal-01551326
%U https://inria.hal.science/hal-01551326
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-AICT
%~ IFIP-TC
%~ IFIP-TC10
%~ IFIP-NPC
%~ IFIP-WG10-3
%~ IFIP-LNCS-7513