@inproceedings{karmani:hal-01551326,
  TITLE = {{Design of a Reliable XOR-XNOR Circuit for Arithmetic Logic Units}},
  AUTHOR = {Karmani, Mouna and Khedhiri, Chiraz and Hamdi, Belgacem and Rahmani, Amir-Mohammad and Man, Ka Lok and Wan, Kaiyu},
  URL = {https://inria.hal.science/hal-01551326},
  NOTE = {Part 12: DATICS},
  BOOKTITLE = {{9th International Conference on Network and Parallel Computing (NPC)}},
  ADDRESS = {Gwangju, South Korea},
  EDITOR = {James J. Park and Albert Zomaya and Sang-Soo Yeo and Sartaj Sahni},
  PUBLISHER = {{Springer}},
  SERIES = {Network and Parallel Computing},
  VOLUME = {LNCS-7513},
  PAGES = {516-523},
  YEAR = {2012},
  MONTH = Sep,
  DOI = {10.1007/978-3-642-35606-3\_61},
  KEYWORDS = {XOR-XNOR circuits ; Concurrent Error Detection ; fault-secure property ; self-testing property ; fault model},
  PDF = {https://inria.hal.science/hal-01551326/file/978-3-642-35606-3_61_Chapter.pdf},
  HAL_ID = {hal-01551326},
  HAL_VERSION = {v1},
}