%0 Conference Proceedings
%T Building a Flexible and Scalable Virtual Hardware Data Plane
%+ Graduate School of the Chinese Academy of Sciences (GSCAS)
%+ Institute of Computing Technology [Beijing] (ICT)
%A Liu, Junjie
%A Xie, Yingke
%A Xie, Gaogang
%A Luo, Layong
%A Zhang, Fuxing
%A Wu, Xiaolong
%A Ning, Qingsong
%A Guan, Hongtao
%Z Part 4: Virtualization and Cloud Services
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B 11th International Networking Conference (NETWORKING)
%C Prague, Czech Republic
%Y Robert Bestak
%Y Lukas Kencl
%Y Li Erran Li
%Y Joerg Widmer
%Y Hao Yin
%I Springer
%3 NETWORKING 2012
%V LNCS-7289
%N Part I
%P 205-216
%8 2012-05-21
%D 2012
%R 10.1007/978-3-642-30045-5_16
%K Network Virtualization
%K Virtual Data Plane
%K FPGA
%Z Computer Science [cs]
%Z Computer Science [cs]/Networking and Internet Architecture [cs.NI]Conference papers
%X Network virtualization which enables the coexistence of multiple networks in shared infrastructure adds extra requirements on data plane of router. Software based virtual data plane is inferior in performance, whereas, hardware based virtual data plane is hard to achieve flexibility and scalability. In this paper, using FPGA (Field Program Gate Array) and TCAM (Ternary Content Addressable Memory), we design and implement a virtual hardware data plane achieving high performance, flexibility and scalability simultaneously. The data plane uses a 5-stage pipeline design. The procedure of packet processing is unified with TCAM based rule matching and action based packet processing. The hardware data plane can be easily configured to support multiple VDP (Virtual Data Plane) instances. And in each VDP instance, the pattern of packet processing can be flexibly configured. Also, it can achieve seamless migration of VDP instance between software and hardware. The hardware data plane also provides a 4-channel high-performance DMA engine which largely reduces packet acquisition overhead on software. So that software can be more involved in customized packet processing.
%G English
%Z TC 6
%2 https://inria.hal.science/hal-01531130/document
%2 https://inria.hal.science/hal-01531130/file/978-3-642-30045-5_16_Chapter.pdf
%L hal-01531130
%U https://inria.hal.science/hal-01531130
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-TC
%~ IFIP-TC6
%~ IFIP-LNCS-7289
%~ IFIP-NETWORKING