%0 Conference Proceedings
%T Speeding Up Galois Field Arithmetic on Intel MIC Architecture
%+ Computer School
%+ Inspur Electronic Information Industry [Beijing]
%A Feng, Kai
%A Ma, Wentao
%A Huang, Wei
%A Zhang, Qing
%A Gong, Yili
%Z Part 3: Session 3: Parallel Architectures
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B 10th International Conference on Network and Parallel Computing (NPC)
%C Guiyang, China
%Y Ching-Hsien Hsu
%Y Xiaoming Li
%Y Xuanhua Shi
%Y Ran Zheng
%I Springer
%3 Network and Parallel Computing
%V LNCS-8147
%P 143-154
%8 2013-09-19
%D 2013
%R 10.1007/978-3-642-40820-5_13
%K Galois Field Arithmetic
%K MIC Architecture
%K SIMD
%K OpenMP
%K Speedup
%Z Computer Science [cs]Conference papers
%X Galois Field arithmetic is the basis of LRC, RS and many other erasure coding approaches. Traditional implementations of Galois Field arithmetic use multiplication tables or discrete logarithms, which limit the speed of its computation. The Intel Many Integrated Core (MIC) Architecture provides 60 cores on chip and very wide 512-bit SIMD instructions, attractive for data intensive applications. This paper demonstrates how to leverage SIMD instructions and shared memory multiprocessing on MIC to perform Galois Field arithmetic. The experiments show that the performance of the computation is significantly enhanced.
%G English
%2 https://inria.hal.science/hal-01513765/document
%2 https://inria.hal.science/hal-01513765/file/978-3-642-40820-5_13_Chapter.pdf
%L hal-01513765
%U https://inria.hal.science/hal-01513765
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-NPC
%~ IFIP-LNCS-8147