%0 Conference Proceedings
%T Fast Software Polynomial Multiplication on ARM Processors Using the NEON Engine
%+ Universidade Estadual de Campinas =  University of Campinas (UNICAMP)
%A Câmara, Danilo
%A Gouvêa, Conrado
%A López, Julio
%A Dahab, Ricardo
%Z Part 2: Security Engineering
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B 1st Cross-Domain Conference and Workshop on Availability, Reliability, and Security in Information Systems (CD-ARES)
%C Regensburg, Germany
%Y Alfredo Cuzzocrea
%Y Christian Kittl
%Y Dimitris E. Simos
%Y Edgar Weippl
%Y Lida Xu
%I Springer
%3 Security Engineering and Intelligence Informatics
%V LNCS-8128
%P 137-154
%8 2013-09-02
%D 2013
%K binary field arithmetic
%K ARM NEON
%K elliptic curve cryptography
%K authenticated encryption
%K software implementation
%Z Computer Science [cs]
%Z Humanities and Social Sciences/Library and information sciencesConference papers
%X Efficient algorithms for binary field operations are required in several cryptographic operations such as digital signatures over binary elliptic curves and encryption. The main performance-critical operation in these fields is the multiplication, since most processors do not support instructions to carry out a polynomial multiplication. In this paper we describe a novel software multiplier for performing a polynomial multiplication of two 64-bit binary polynomials based on the VMULL instruction included in the NEON engine supported in many ARM processors. This multiplier is then used as a building block to obtain a fast software multiplication in the binary field $\mathbb{F}_{2^m}$, which is up to 45% faster compared to the best known algorithm. We also illustrate the performance improvement in point multiplication on binary elliptic curves using the new multiplier, improving the performance of standard NIST curves at the 128- and 256-bit levels of security. The impact on the GCM authenticated encryption scheme is also studied, with new speed records. We present timing results of our software implementation on the ARM Cortex-A8, A9 and A15 processors.
%G English
%2 https://inria.hal.science/hal-01506572/document
%2 https://inria.hal.science/hal-01506572/file/978-3-642-40588-4_10_Chapter.pdf
%L hal-01506572
%U https://inria.hal.science/hal-01506572
%~ SHS
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-TC
%~ IFIP-TC5
%~ IFIP-WG
%~ IFIP-TC8
%~ IFIP-CD-ARES
%~ IFIP-WG8-4
%~ IFIP-WG8-9
%~ IFIP-LNCS-8128