%0 Conference Proceedings
%T Joint Algorithm Developing and System-Level Design: Case Study on Video Encoding
%+ Northeastern University [Boston]
%A Zhang, Jiaxing
%A Schirner, Gunar
%Z Part 1: Design Methodologies
%< avec comité de lecture
%( IFIP Advances in Information and Communication Technology
%B 4th International Embedded Systems Symposium (IESS)
%C Paderborn, Germany
%Y Gunar Schirner
%Y Marcelo Götz
%Y Achim Rettberg
%Y Mauro C. Zanella
%Y Franz J. Rammig
%I Springer
%3 Embedded Systems: Design, Analysis and Verification
%V AICT-403
%P 26-38
%8 2013-06-17
%D 2013
%R 10.1007/978-3-642-38853-8_3
%Z Computer Science [cs]Conference papers
%X System-Level Design Environments (SLDEs) are often utilized for tackling the design complexity of modern embedded systems. SLDEs typically start with a specification capturing core algorithms. Algorithm development itself largely occurs in Algorithm Design Environments (ADE) with little or no hardware concern. Currently, algorithm and system design environments are disjoint; system level specifications are manually implemented which leads to the specification gap.In this paper, we bridge algorithm and system design environments creating a unified design flow facilitating algorithm and system co-design. It enables algorithm realizations over heterogeneous platforms, while still tuning the algorithm according to platform needs. Our design flow starts with algorithm design in Simulink, out of which a System Level Design Language (SLDL)-based specification is synthesized. This specification then is used for design space exploration across heterogeneous target platforms and abstraction levels, and, after identifying a suitable platform, synthesized to HW/SW implementations. It realizes a unified development cycle across algorithm modeling and system-level design with quick responses to design decisions on algorithm-, specification- and system exploration level. It empowers the designer to combine analysis results across environments, apply cross layer optimizations, which will yield an overall optimized design through rapid design iterations.We demonstrate the benefits on a MJPEG video encoder case study, showing early computation/communication estimation and rapid prototyping from Simulink models. Results from Virtual Platform performance analysis enable the algorithm designer to improve model structure to better match the heterogeneous platform in an efficient and fast design cycle. Through applying our unified design flow, an improved HW/SW is found yielding 50% performance gain compared to a pure software solution.
%G English
%Z TC 10
%2 https://inria.hal.science/hal-01466691/document
%2 https://inria.hal.science/hal-01466691/file/978-3-642-38853-8_3_Chapter.pdf
%L hal-01466691
%U https://inria.hal.science/hal-01466691
%~ IFIP
%~ IFIP-AICT
%~ IFIP-TC
%~ IFIP-TC10
%~ IFIP-AICT-403
%~ IFIP-IESS