%0 Conference Proceedings
%T Automated Identification of Performance Bottleneck on Embedded Systems for Design Space Exploration
%+ Nagoya University
%+ Ritsumeikan University
%A Ando, Yuki
%A Shibata, Seiya
%A Honda, Shinya
%A Tomiyama, Hiroyuki
%A Takada, Hiroaki
%Z Part 4: Performance Analysis
%< avec comité de lecture
%( IFIP Advances in Information and Communication Technology
%B 4th International Embedded Systems Symposium (IESS)
%C Paderborn, Germany
%Y Gunar Schirner
%Y Marcelo Götz
%Y Achim Rettberg
%Y Mauro C. Zanella
%Y Franz J. Rammig
%I Springer
%3 Embedded Systems: Design, Analysis and Verification
%V AICT-403
%P 171-180
%8 2013-06-17
%D 2013
%R 10.1007/978-3-642-38853-8_16
%Z Computer Science [cs]Conference papers
%X Embedded systems usually have strict resource and performance constraints. Designers often need to improve the system design so that the system satisfies those constraints. In such case, performance bottlenecks should be identified and improved effectively. In this paper, we present a method to identify performance bottlenecks. Our method automatically identifies not only the bottlenecks but also a list of improvement rates of bottlenecks that is necessary for the system to satisfy design constraints. With the list of improvement rates, designers easily consider how to improve the bottlenecks. A case study on AES encryption and decryption application shows effectiveness of our method.
%G English
%Z TC 10
%2 https://inria.hal.science/hal-01466671/document
%2 https://inria.hal.science/hal-01466671/file/978-3-642-38853-8_16_Chapter.pdf
%L hal-01466671
%U https://inria.hal.science/hal-01466671
%~ IFIP
%~ IFIP-AICT
%~ IFIP-TC
%~ IFIP-TC10
%~ IFIP-AICT-403
%~ IFIP-IESS