%0 Conference Proceedings
%T Trinocular Stereo Vision Using a Multi Level Hierarchical Classification Structure
%+ Hasselt University (UHasselt)
%+ Zhejiang University
%A Motten, Andy
%A Claesen, Luc
%A Pan, Yun
%< avec comité de lecture
%( IFIP Advances in Information and Communication Technology
%B 20th International Conference on Very Large Scale Integration (VLSI-SoC)
%C Santa Cruz, CA, United States
%Y Andreas Burg
%Y Ayse Coskun
%Y Matthew Guthaus
%Y Srinivas Katkoori
%Y Ricardo Reis
%I Springer
%3 VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design
%V AICT-418
%P 45-63
%8 2012-08-07
%D 2012
%R 10.1007/978-3-642-45073-0_3
%K trinocular stereo camera
%K real-time matching
%K confidence metric
%K computer vision
%K system-on-chip
%K FPGA
%K SoC
%Z Computer Science [cs]Conference papers
%X A real-time trinocular stereo vision processor is proposed which combines a window matching architecture with a classification architecture. A pair wise segmented window matching for both the center-right and center-left image pairs as their scaled down image pairs is performed. The resulting cost functions are combined which results into nine different cost curves. A multi level hierarchical classifier is used to select the most promising disparity value. The classifier makes use of features provided by the calculated cost curves and the pixels’ spatial neighborhood information. Evaluation and classifier training has been performed using an indoor dataset. The system is prototyped on an FPGA board equipped with three CMOS cameras. Special care has been taken to reduce the latency and the memory footprint.
%G English
%Z TC 10
%Z WG 10.5
%2 https://inria.hal.science/hal-01456961/document
%2 https://inria.hal.science/hal-01456961/file/978-3-642-45073-0_3_Chapter.pdf
%L hal-01456961
%U https://inria.hal.science/hal-01456961
%~ IFIP
%~ IFIP-AICT
%~ IFIP-TC
%~ IFIP-WG
%~ IFIP-VLSISOC
%~ IFIP-TC10
%~ IFIP-WG10-5
%~ IFIP-AICT-418