%0 Conference Proceedings
%T Acceleration of Blender Cycles Path-Tracing Engine Using Intel Many Integrated Core Architecture
%+ Technical University of Ostrava [Ostrava] (VSB)
%A Jaroš, Milan
%A Říha, Lubomír
%A Strakoš, Petr
%A Karásek, Tomáš
%A Vašatová, Alena
%A Jarošová, Marta
%A Kozubek, Tomáš
%Z Part 2: Algorithms
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B 14th Computer Information Systems and Industrial Management (CISIM)
%C Warsaw, Poland
%Y Khalid Saeed
%Y Władysław Homenda
%I Springer
%3 Computer Information Systems and Industrial Management
%V LNCS-9339
%P 86-97
%8 2015-09-24
%D 2015
%R 10.1007/978-3-319-24369-6_7
%K Intel xeon phi
%K Blender Cycles
%K Quasi-Monte Carlo
%K Path Tracing
%K Rendering
%Z Computer Science [cs]
%Z Humanities and Social Sciences/Library and information sciencesConference papers
%X This paper describes the acceleration of the most computationally intensive kernels of the Blender rendering engine, Blender Cycles, using Intel Many Integrated Core architecture (MIC). The proposed parallelization, which uses OpenMP technology, also improves the performance of the rendering engine when running on multi-core CPUs and multi-socket servers. Although the GPU acceleration is already implemented in Cycles, its functionality is limited. Our proposed implementation for MIC architecture contains all features of the engine with improved performance. The paper presents performance evaluation for three architectures: multi-socket server, server with MIC (Intel Xeon Phi 5100p) accelerator and server with GPU accelerator (NVIDIA Tesla K20m).
%G English
%Z TC 8
%2 https://inria.hal.science/hal-01444507/document
%2 https://inria.hal.science/hal-01444507/file/978-3-319-24369-6_7_Chapter.pdf
%L hal-01444507
%U https://inria.hal.science/hal-01444507
%~ SHS
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-TC
%~ IFIP-TC8
%~ IFIP-CISIM
%~ IFIP-LNCS-9339