%0 Conference Proceedings
%T Increasing Multi-controller Parallelism for Hybrid-Mapped Flash Translation Layers
%+ National Taiwan University of Science and Technology
%A Sung, Hung-Yi
%A Wu, Chin-Hsien
%Z Part 6: Poster Sessions
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B 11th IFIP International Conference on Network and Parallel Computing (NPC)
%C Ilan, Taiwan
%Y Ching-Hsien Hsu
%Y Xuanhua Shi
%Y Valentina Salapura
%I Springer
%3 Network and Parallel Computing
%V LNCS-8707
%P 567-570
%8 2014-09-18
%D 2014
%R 10.1007/978-3-662-44917-2_54
%Z Computer Science [cs]Conference papers
%X Nowadays, the architecture of solid-state drives (SSDs) is using multiple controllers to efficiently handle NAND flash memory chips. Several flash translation layers (FTLs) have been proposed to improve the overall performance of NAND flash memory. Therefore, the collaboration of FTLs and the multi-controller design of SSDs will become an important research topic. In this paper, we will propose a method to increase multi-controller parallelism for hybrid-mapped flash translation layers.
%G English
%Z TC 10
%Z WG 10.3
%2 https://inria.hal.science/hal-01403146/document
%2 https://inria.hal.science/hal-01403146/file/978-3-662-44917-2_54_Chapter.pdf
%L hal-01403146
%U https://inria.hal.science/hal-01403146
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-AICT
%~ IFIP-TC
%~ IFIP-LNCS-8707
%~ IFIP-TC10
%~ IFIP-NPC
%~ IFIP-WG10-3