@inproceedings{moradi:hal-01383730,
  TITLE = {{8T-SRAM cell with Improved Read and Write Margins in 65 nm CMOS Technology}},
  AUTHOR = {Moradi, Farshad and Tohidi, Mohammad and Zeinali, Behzad and Madsen, Jens K.},
  URL = {https://inria.hal.science/hal-01383730},
  BOOKTITLE = {{22th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC 2014)}},
  ADDRESS = {Playa del Carmen, Mexico},
  EDITOR = {Luc Claesen and Maria-Teresa Sanz-Pascual and Ricardo Reis and Arturo Sarmiento-Reyes},
  SERIES = {VLSI-SoC: Internet of Things Foundations},
  VOLUME = {AICT-464},
  PAGES = {95-109},
  YEAR = {2014},
  MONTH = Oct,
  DOI = {10.1007/978-3-319-25279-7\_6},
  KEYWORDS = {SRAM ; Subthreshold ; Low-power ; Write margin},
  PDF = {https://inria.hal.science/hal-01383730/file/371768_1_En_6_Chapter.pdf},
  HAL_ID = {hal-01383730},
  HAL_VERSION = {v1},
}