%0 Conference Proceedings
%T Design of a Fully Differential Power Output Stage for a Class D Audio Amplifier Using a Single-Ended Power Supply
%+ Universidade de Lisboa = University of Lisbon (ULISBOA)
%A Leitão, Pedro, V.
%A Melo, João, De
%A Paulino, Nuno
%Z Part 19: Electronics: Amplifiers
%< avec comité de lecture
%( IFIP Advances in Information and Communication Technology
%B 4th Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS)
%C Costa de Caparica, Portugal
%Y Luis M. Camarinha-Matos
%Y Slavisa Tomic
%Y Paula Graça
%I Springer
%3 Technological Innovation for the Internet of Things
%V AICT-394
%P 565-572
%8 2013-04-15
%D 2013
%R 10.1007/978-3-642-37291-9_61
%K Class D Audio Amplifier
%K Output Stage
%K Gate Driver
%Z Computer Science [cs]Conference papers
%X This paper presents a full-bridge discrete power output stage for a Class D audio amplifier using a single-ended power supply. The circuit receives a digital control signal with 5 V of amplitude and it generates a floating differential output voltage up to 20 V of amplitude from a single 20 V power supply voltage. Using as control signal a pulse density modulation (PDM) wave generated by an optimized 3rd order continuous-time (CT) sigma delta modulator (ΣΔM), the system achieves a signal-to-noise-plus-distortion ratio (SNDR) of 83.1 dB, total harmonic distortion (THD) of -89 dB and a power efficiency of 92 %, while delivering 11 W over an 8-Ω load with a signal bandwidth of 20 kHz and a sampling frequency of 1.28 MHz.
%G English
%Z TC 5
%Z WG 5.5
%2 https://hal.science/hal-01348803/document
%2 https://hal.science/hal-01348803/file/978-3-642-37291-9_61_Chapter.pdf
%L hal-01348803
%U https://hal.science/hal-01348803
%~ IFIP
%~ IFIP-AICT
%~ IFIP-TC
%~ IFIP-TC5
%~ IFIP-WG
%~ IFIP-WG5-5
%~ IFIP-DOCEIS
%~ IFIP-AICT-394