%0 Conference Proceedings
%T A Very Compact Hardware Implementation of the KASUMI Block Cipher
%+ Fujitsu Laboratories LTD.
%A Yamamoto, Dai
%A Itoh, Kouichi
%A Yajima, Jun
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B 4th IFIP WG 11.2 International Workshop on Information Security Theory and Practices: Security and Privacy of Pervasive Systems and Smart Devices (WISTP)
%C Passau, Germany
%Y Pierangela Samarati; Michael Tunstall; Joachim Posegga; Konstantinos Markantonakis; Damien Sauveron
%I Springer
%3 Information Security Theory and Practices. Security and Privacy of Pervasive Systems and Smart Devices
%V LNCS-6033
%P 293-307
%8 2010-04-12
%D 2010
%R 10.1007/978-3-642-12368-9_23
%K Block cipher
%K KASUMI
%K Hardware
%K ASIC
%K FPGA
%K Compact Implementation
%Z Computer Science [cs]/Digital Libraries [cs.DL]Conference papers
%X For mobile devices, this paper proposes a compact hardware (H/W) implementation for the KASUMI block cipher, which is the 3GPP standard encryption algorithm. In [4], Yamamoto et al. proposed the method of reducing temporary registers for the MISTY1 FO function (YYI-08), and implemented a very compact MISTY1 H/W. This paper aims to design the smallest KASUMI H/W by the application of YYI-08 to KASUMI, which has a similarly structured MISTY1 FO function. We discussed the applicability and found the problems on register competition and logical equivalence in the simple application, so we propose the new YYI-08 improved for KASUMI and the compact H/W architecture. According to our logic synthesis on a 0.11-μm ASIC process, the gate size is 2.99 Kgates, which is the smallest as far as we know.
%G English
%2 https://inria.hal.science/hal-01056077/document
%2 https://inria.hal.science/hal-01056077/file/60330295.pdf
%L hal-01056077
%U https://inria.hal.science/hal-01056077
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-LNCS-6033
%~ IFIP-TC
%~ IFIP-TC11
%~ IFIP-WISTP
%~ IFIP-WG11-2
%~ IFIP-2010