%0 Conference Proceedings
%T Adaptive Line Size Cache for Irregular References on Cell Multicore Processor
%+ University of Science and Technology Beijing [Beijing] (USTB)
%A Cao, Qian
%A Zhao, Chongchong
%A Chen, Junxiu
%A Zhang, Yunxing
%A Chen, Yi
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B IFIP International Conference on Network and Parallel Computing (NPC)
%C Zhengzhou, China
%Y Chen Ding; Zhiyuan Shao; Ran Zheng
%I Springer
%3 Network and Parallel Computing
%V LNCS-6289
%P 314-328
%8 2010-09-13
%D 2010
%R 10.1007/978-3-642-15672-4_27
%K Adaptive
%K Software cache
%K Irregular reference
%K Cell processor
%Z Computer Science [cs]/Digital Libraries [cs.DL]Conference papers
%X Software cache promises to achieve programmability on Cell processor. However, irregular references couldn't achieve a considerable performance improvement since the cache line is always set to a specific size. In this paper, we propose an adaptive cache line prefetching strategy which continuously adjusts cache line size during application execution. Therefore, the transferred data is decreased significantly. Moreover, a corresponding software cache - adaptive line size cache is designed. It introduces a hybrid Tag Entry Arrays, with each mapping to a different line size. It's a hierarchical design in that the misshandler is not invoked immediately when an address is a miss in the short line Tag Entry Array. Instead, the long line Tag Entry Array is checked first, which significantly increases the hit rate. Evaluations indicate that improvement due to the adaptive cache line strategy translates into 3.29 to 5.73 speedups compared to the traditional software cache approach.
%G English
%2 https://inria.hal.science/hal-01054976/document
%2 https://inria.hal.science/hal-01054976/file/Adaptive_Line_Size_Cache_for_Irregular_References_on_Cell_Multicore_Processor.pdf
%L hal-01054976
%U https://inria.hal.science/hal-01054976
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-LNCS-6289
%~ IFIP-NPC
%~ IFIP-2010