%0 Conference Proceedings
%T Software-Hardware Cooperative DRAM Bank Partitioning for Chip Multiprocessors
%+ Key Laboratory of Computer System and Architecture
%+ Graduate University of Chinese [Beijing] (UCAS)
%+ School of Computer Science and Engineering
%A Mi, Wei
%A Feng, Xiaobing
%A Xue, Jingling
%A Jia, Yaocang
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B IFIP International Conference on Network and Parallel Computing (NPC)
%C Zhengzhou, China
%Y Chen Ding; Zhiyuan Shao; Ran Zheng
%I Springer
%3 Network and Parallel Computing
%V LNCS-6289
%P 329-343
%8 2010-09-13
%D 2010
%R 10.1007/978-3-642-15672-4_28
%K Row Buffer Locality
%K Cache Locality
%K Address Mapping
%Z Computer Science [cs]/Digital Libraries [cs.DL]Conference papers
%X DRAM row buffer conflicts can increase the memory access latency significantly for single-threaded applications. In a chip multiprocessor system, multiple applications competing for DRAM will suffer additional row buffer conflicts due to interthread interference. This paper presents a new hardware and software cooperative DRAM bank partitioning method that combines page coloring and XOR cache mapping to evaluate the benefit potential of reducing interthread interference. Using SPECfp2000 as our benchmarks, our simulation results show that our scheme can boost the performance of the most benchmark combinations tested, with the speedups of up to 13%, 14% and 8.06% observed for two cores (with 16 banks), two cores (with 32 banks) and four cores (with 32 banks).
%G English
%2 https://inria.hal.science/hal-01054975/document
%2 https://inria.hal.science/hal-01054975/file/NPC_pape-1569314947_in_EDAS.pdf
%L hal-01054975
%U https://inria.hal.science/hal-01054975
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-LNCS-6289
%~ IFIP-NPC
%~ IFIP-2010