%0 Conference Proceedings
%T The Core Degree Based Tag Reduction on Chip Multiprocessor to Balance Energy Saving and Performance Overhead
%+ Huazhong University of Science and Technology [Wuhan] (HUST)
%+ University of Aizu
%+ University of Waterloo [Waterloo]
%+ Shanghai Jiao Tong University [Shanghai]
%A Zheng, Long
%A Dong, Mianxiong
%A Jin, Hai
%A Guo, Minyi
%A Guo, Song
%A Tu, Xuping
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B IFIP International Conference on Network and Parallel Computing (NPC)
%C Zhengzhou, China
%Y Chen Ding; Zhiyuan Shao; Ran Zheng
%I Springer
%3 Network and Parallel Computing
%V LNCS-6289
%P 358-372
%8 2010-09-13
%D 2010
%R 10.1007/978-3-642-15672-4_30
%Z Computer Science [cs]/Digital Libraries [cs.DL]Conference papers
%X Tag reduction is an approach to save energy of the cache system in a processor. Our previous work described that it can save more energy on a Chip Multiprocessor (CMP) than on a single-core processor. In this paper, we further investigate the problem on balancing energy saving and performance overhead when tag reduction is used for the low power Chip Multiprocessor (CMP). We first introduce the core degree concept which is defined as the number of cores that tag reduction can use for each thread. We then propose a core degree based tag approach that is to optimize the core degree such that the best balance of energy and performance can be achieved. In particular, as the basis for such optimization, the theoretical upper bounds of the energy savings and performance overhead are decided as function of the core degree. In our experiments, we use a 16-core CMP for example. In order to obtain the energy consumption and performance overhead with various core degrees, we construct an experimental environment, which is based on the Linux operating system. With the experimental environment, benchmarks of SPEC CPU2006 are used to evaluate our core degree based tag reduction. Finally, the experimental results show that the most desired balance of energy saving and performance overhead is achieved when core degree is set to 6.
%G English
%2 https://inria.hal.science/hal-01054972/document
%2 https://inria.hal.science/hal-01054972/file/NPC10-1569319175_in_EDAS.pdf
%L hal-01054972
%U https://inria.hal.science/hal-01054972
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-LNCS-6289
%~ IFIP-NPC
%~ IFIP-2010