%0 Conference Proceedings
%T A Methodology for Design of Unbuffered Router Microarchitecture for S-Mesh NoC
%+ Henan Electric Power Research Institute
%+ Department of Electronic Science & Technology,Huazhong
%+ Henan Electric Power Industrial School
%A Liu, Hao
%A Cao, Feifei
%A Liu, Dongsheng
%A Zou, Xuecheng
%A Zhang, Zhigang
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B IFIP International Conference on Network and Parallel Computing (NPC)
%C Zhengzhou, China
%Y Chen Ding; Zhiyuan Shao; Ran Zheng
%I Springer
%3 Network and Parallel Computing
%V LNCS-6289
%P 442-451
%8 2010-09-13
%D 2010
%R 10.1007/978-3-642-15672-4_37
%K NoC
%K separated-mesh (S-mesh)
%K unbuffered
%K low-latency
%K low-cost
%Z Computer Science [cs]/Digital Libraries [cs.DL]Conference papers
%X Currently, most of Network on-Chip (NoC) architectures have some limitation in routing decisions. And it makes router nodes overloaded, and sequentially forms deadlock, livelock and congestion. A simple unbuffered router microarchitecture for S-mesh NoC architecture is proposed in this paper. Unbuffered router transforms message without making routing decision. Simulation results showed that S-mesh could get optimal performance in message latency compared with 2D-mesh, Butterfly and Octagon NoC architectures. The Design Compiler synthesis results showed that unbuffered router has obvious advantages on area, and it gets higher operation speed.
%G English
%2 https://inria.hal.science/hal-01054965/document
%2 https://inria.hal.science/hal-01054965/file/NPC10-IWNoC-105.pdf
%L hal-01054965
%U https://inria.hal.science/hal-01054965
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-LNCS-6289
%~ IFIP-NPC
%~ IFIP-2010