%0 Conference Proceedings
%T MPSoC Architecture-Aware Automatic NoC Topology Design
%+ Lab-STICC_UBS_CACS_MOCS
%A Dafali, Rachid
%A Diguet, Jean-Philippe
%< avec comité de lecture
%( Lecture Notes in Computer Science
%B IFIP International Conference on Network and Parallel Computing (NPC)
%C Zhengzhou, China
%Y Chen Ding; Zhiyuan Shao; Ran Zheng
%I Springer
%3 Network and Parallel Computing
%V LNCS-6289
%P 470-480
%8 2010-09-13
%D 2010
%R 10.1007/978-3-642-15672-4_40
%K Application Specific Network
%K Network-on-Chip
%K Topology Generation
%K Mapping
%Z Computer Science [cs]/Digital Libraries [cs.DL]Conference papers
%X This paper presents a methodology for the automatic definition of NoC topology according to application and architecture requirements. The proposed solution, which has been implemented as a new step of our NoC design flow, results from the analysis of real concerns and demands from designers. The main contribution lies in the fact that we customize the method according to multiprocessor architecture models and associated memory organizations. A real-life H264 example has been used to compare synthesis results for NoCs generated by our tool, with automatic topology selection with well-known efficient topologies, which wer manually specified. Results clearly show the efficiency of our approach.
%G English
%2 https://inria.hal.science/hal-01054961/document
%2 https://inria.hal.science/hal-01054961/file/mpsoc_architecture_aware_automatic_noc_topology_design.pdf
%L hal-01054961
%U https://inria.hal.science/hal-01054961
%~ UNIV-BREST
%~ INSTITUT-TELECOM
%~ CNRS
%~ UNIV-UBS
%~ UBS
%~ LAB-STICC_UBS
%~ ENIB
%~ LAB-STICC_ENIB
%~ IFIP-LNCS
%~ IFIP
%~ IFIP-LNCS-6289
%~ LAB-STICC
%~ IFIP-NPC
%~ IFIP-2010
%~ INSTITUTS-TELECOM